Invention Grant
- Patent Title: Memory cell biasing techniques during a read operation
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Application No.: US17741136Application Date: 2022-05-10
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Publication No.: US12237002B2Publication Date: 2025-02-25
- Inventor: Andrea Locatelli , Giorgio Servalli , Angelo Visconti
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: G11C11/4096
- IPC: G11C11/4096 ; G11C11/22 ; G11C11/406 ; G11C11/4091 ; G11C11/4097

Abstract:
Methods, systems, and devices for biasing a memory cell during a read operation are described. For example, a memory device may bias a memory cell to a first voltage (e.g., a read voltage) during an activation phase of a read operation. After biasing the memory cell to the first voltage, the memory device may bias the memory cell to a second voltage greater than the first voltage (e.g., a write voltage) during the activation phase of the read operation. After biasing the memory cell to the second voltage, the memory device may initiate a refresh phase of the read operation. Based on a value stored by the memory cell prior to biasing the memory cell to the first voltage, the memory device may initiate a precharge phase of the read operation.
Public/Granted literature
- US20220270667A1 MEMORY CELL BIASING TECHNIQUES DURING A READ OPERATION Public/Granted day:2022-08-25
Information query
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