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公开(公告)号：US20230397436A1
公开(公告)日：2023-12-07
申请号：US18204077
申请日：2023-05-31
发明人： Giorgio Servalli , Marcello Mariani
CPC分类号： H10B53/30 , G11C11/2273 , H10B53/40
摘要： Methods, systems, and devices for a ferroelectric memory architecture are described. A memory architecture may include a gap region between memory cells to reduce a capacitance between plates coupled with the memory cells. The gap region may include a fluid, such as air, which may have a relatively low dielectric constant to reduce a capacitance between plates and reduce (e.g., eliminate) undesirable coupling between plates during memory operations. Implementing the gap region between memory cells enables a memory device to increase speed and reduce resource consumption associated with memory operations
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公开(公告)号：US11742002B2
公开(公告)日：2023-08-29
申请号：US17550535
申请日：2021-12-14
CPC分类号： G11C7/1048 , G11C7/222 , G11C11/2273 , G11C11/2275 , G11C11/2297
摘要： Systems, apparatuses, and methods related to memory activation timing management are described herein. In an examples, memory activation timing management can include receiving a first command associated with a set of memory cells, activating the set of memory cells to perform a memory access responsive to the first command, pre-charging the set of memory cells associated with the first command, receiving a second command associated with the set of memory cells, determining that the set of memory cells associated with the first command is a recently activated set of the plurality of sets of memory cells, imparting a delay, and applying a sensing voltage to the set of memory cells associated with the second command to perform a memory access responsive to the second command.
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公开(公告)号：US11672128B2
公开(公告)日：2023-06-06
申请号：US16933134
申请日：2020-07-20
发明人： Marcello Mariani , Giorgio Servalli
IPC分类号： H01L27/11507 , H01L49/02 , H01L27/11504 , H01L23/60
CPC分类号： H01L27/11507 , H01L23/60 , H01L27/11504 , H01L28/55 , H01L28/60
摘要： Some embodiments include an integrated assembly having a row of conductive posts. The conductive posts are spaced from one another by gaps. Leaker device material extends is within at least some of the gaps. An insulative material is along sidewalls of the conductive posts. A conductive structure is over the conductive posts. The conductive structure has downward projections extending into at least some of the gaps. The leaker device material is configured as segments along sides of the downward projections and extends from the sides to one or more of the conductive posts. Some embodiments include methods of forming integrated assemblies.
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公开(公告)号：US20230027308A1
公开(公告)日：2023-01-26
申请号：US17381040
申请日：2021-07-20
IPC分类号： H01L27/11512 , G11C11/22 , H01L27/11504 , H01L27/11507 , H01L27/11509
摘要： Some embodiments include an integrated assembly having a first bottom electrode adjacent to a second bottom electrode. An intervening region is directly between the first and second bottom electrodes. Capacitor-insulative-material is adjacent to the first and second bottom electrodes. The capacitor-insulative-material is substantially not within the intervening region. Top-electrode-material is adjacent to the capacitor-insulative-material. Some embodiments include methods of forming integrated assemblies.
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公开(公告)号：US20220285392A1
公开(公告)日：2022-09-08
申请号：US17189594
申请日：2021-03-02
发明人： Giorgio Servalli , Marcello Mariani
IPC分类号： H01L27/11597 , H01L27/11504 , H01L27/11514 , H01L27/11587
摘要： Some embodiments include an integrated assembly having pillars arranged in an array. The pillars have channel regions between upper and lower source/drain regions. Gating structures are proximate to the channel regions and extend along a row direction. Digit lines are beneath the pillars, extend along a column direction, and are coupled with the lower source/drain regions. Linear structures are above the pillars and extend along the column direction. Bottom electrodes are coupled with the upper source/drain regions. The bottom electrodes have horizontal segments adjacent the upper source/drain regions and have vertical segments extending upwardly from the horizontal segments. The vertical segments are adjacent to lateral sides of the linear structures. Ferroelectric-insulative-material and top-electrode-material are over the bottom electrodes. A slit passes through the top-electrode-material, is directly over one of the linear structures, and extends along the column direction.
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公开(公告)号：US20220199129A1
公开(公告)日：2022-06-23
申请号：US17550535
申请日：2021-12-14
摘要： Systems, apparatuses, and methods related to memory activation timing management are described herein. In an examples, memory activation timing management can include receiving a first command associated with a set of memory cells, activating the set of memory cells to perform a memory access responsive to the first command, pre-charging the set of memory cells associated with the first command, receiving a second command associated with the set of memory cells, determining that the set of memory cells associated with the first command is a recently activated set of the plurality of sets of memory cells, imparting a delay, and applying a sensing voltage to the set of memory cells associated with the second command to perform a memory access responsive to the second command.
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公开(公告)号：US11355531B1
公开(公告)日：2022-06-07
申请号：US17107242
申请日：2020-11-30
发明人： Marcello Mariani , Giorgio Servalli
IPC分类号： H01L27/13 , H01L21/84 , H01L27/12 , H01L27/115 , H01L27/105
摘要： A method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above insulator material. A mask is used to subtractively etch both the transistor material and thereafter the insulator material to form a plurality of pillars that individually comprise the transistor material and the insulator material. The insulator material is laterally-recessed from opposing lateral sides of individual of the pillars selectively relative to the transistor material of the individual pillars. The individual pillars are formed to comprise a first capacitor electrode that is in void space formed from the laterally recessing. Capacitors are formed that individually comprise the first capacitor electrode of the individual pillars. A capacitor insulator is aside the first capacitor electrode of the individual pillars and a second capacitor electrode is laterally-outward of the capacitor insulator. Vertical transistors are formed above the capacitors and individually comprise the transistor material of the individual pillars. Other aspects, including structure independent of method, are disclosed.
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公开(公告)号：US11348635B2
公开(公告)日：2022-05-31
申请号：US16834941
申请日：2020-03-30
IPC分类号： G11C11/4096 , G11C11/22 , G11C11/4097 , G11C11/406 , G11C11/4091
摘要： Methods, systems, and devices for biasing a memory cell during a read operation are described. For example, a memory device may bias a memory cell to a first voltage (e.g., a read voltage) during an activation phase of a read operation. After biasing the memory cell to the first voltage, the memory device may bias the memory cell to a second voltage greater than the first voltage (e.g., a write voltage) during the activation phase of the read operation. After biasing the memory cell to the second voltage, the memory device may initiate a refresh phase of the read operation. Based on a value stored by the memory cell prior to biasing the memory cell to the first voltage, the memory device may initiate a precharge phase of the read operation.
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公开(公告)号：US20210335793A1
公开(公告)日：2021-10-28
申请号：US16855446
申请日：2020-04-22
发明人： Marcello Mariani , Giorgio Servalli
IPC分类号： H01L27/108 , H01L29/66 , H01L29/78 , H01L21/02 , H01L21/306 , H01L21/308
摘要： A method used in forming an array of memory cells comprises forming lines of top-source/drain-region material, bottom-source/drain-region material, and channel-region material vertically there-between in rows in a first direction. The lines are spaced from one another in a second direction. The top-source/drain-region material, bottom-source/drain-region material, and channel-region material have respective opposing sides. The channel-region material on its opposing sides is laterally recessed in the second direction relative to the top-source/drain-region material and the bottom-source/drain-region material on their opposing sides to form a pair of lateral recesses in the opposing sides of the channel-region material in individual of the rows. After the pair of lateral recesses are formed, the lines of the top-source/drain-region material, the channel-region material, and the bottom-source/drain-region material are patterned in the second direction to comprise pillars of individual transistors. Rows of wordlines are formed in the first direction that individually are operatively aside the channel-region material of individual of the pillars in the pairs of lateral recesses and that interconnect the transistors in that individual row. Other embodiments, including structure independent of method, are disclosed.
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公开(公告)号：US10964372B2
公开(公告)日：2021-03-30
申请号：US16441763
申请日：2019-06-14
摘要： Methods, systems, and devices for memory cell biasing techniques are described. A memory cell may be accessed during an access phase of an access operation. A pre-charge phase of the access phase may be initiated. The memory cell may be biased to a voltage (e.g., a non-zero voltage) after the pre-charge phase. In some examples, the memory cell may be biased to the voltage when a word line is unbiased and the memory cell is isolated from the digit line.
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