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    Memory cell biasing techniques during a read operation
    1.
    发明授权
    Memory cell biasing techniques during a read operation 有权

    公开(公告)号：US12237002B2

    公开(公告)日：2025-02-25

    申请号：US17741136

    申请日：2022-05-10

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Locatelli ,  Giorgio Servalli ,  Angelo Visconti

    IPC: G11C11/4096 ,  G11C11/22 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4097

    Abstract: Methods, systems, and devices for biasing a memory cell during a read operation are described. For example, a memory device may bias a memory cell to a first voltage (e.g., a read voltage) during an activation phase of a read operation. After biasing the memory cell to the first voltage, the memory device may bias the memory cell to a second voltage greater than the first voltage (e.g., a write voltage) during the activation phase of the read operation. After biasing the memory cell to the second voltage, the memory device may initiate a refresh phase of the read operation. Based on a value stored by the memory cell prior to biasing the memory cell to the first voltage, the memory device may initiate a precharge phase of the read operation.

    OPEN PAGE BIASING TECHNIQUES
    2.
    发明申请
    OPEN PAGE BIASING TECHNIQUES 有权

    公开(公告)号：US20210193210A1

    公开(公告)日：2021-06-24

    申请号：US17143800

    申请日：2021-01-07

    Applicant: Micron Technology, Inc.

    Inventor： Angelo Visconti ,  Andrea Locatelli ,  Giorgio Servalli

    IPC: G11C11/22 ,  G06F3/06

    Abstract: Methods, systems, and devices for biasing techniques, such as open page biasing techniques, are described. A memory cell may be accessed during an access phase of an access operation, for example, an open page access operation. An activate pulse may be applied to the memory cell during the access phase. The memory cell may be biased to a non-zero voltage after applying the activate pulse and before a pre-charge phase. The pre-charge phase of the access phase may be initiated after biasing the memory cell to the non-zero voltage.

    Ferroelectric memory cell recovery
    3.
    发明授权
    Ferroelectric memory cell recovery 有权

    公开(公告)号：US09697913B1

    公开(公告)日：2017-07-04

    申请号：US15179695

    申请日：2016-06-10

    Applicant: Micron Technology, Inc.

    Inventor： Marcello Mariani ,  Giorgio Servalli ,  Andrea Locatelli

    IPC: G11C11/22 ,  G11C29/50

    CPC classification number: G11C29/50004 ,  G11C11/2253 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  G11C11/2297

    Abstract: Methods, systems, and devices for recovering fatigued ferroelectric memory cells are described. Recovery voltages may be applied to a ferroelectric memory cell that is fatigued due to repeated access (read or write) operations. The recovery voltage may have a greater amplitude than the access voltage and may include multiple voltage pulses or a constant voltage. The recovery operation may be performed in the background as the memory array operates, or it may be performed when a host device is not actively using the memory array. The recovery operations may be performed periodically or may include discrete series of pulses distributed among several instances.

    MEMORY CELL BIASING TECHNIQUES DURING A READ OPERATION
    4.
    发明申请
    MEMORY CELL BIASING TECHNIQUES DURING A READ OPERATION 有权

    公开(公告)号：US20210304812A1

    公开(公告)日：2021-09-30

    申请号：US16834941

    申请日：2020-03-30

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Locatelli ,  Giorgio Servalli ,  Angelo Visconti

    IPC: G11C11/4096 ,  G11C11/22 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4097

    Abstract: Methods, systems, and devices for biasing a memory cell during a read operation are described. For example, a memory device may bias a memory cell to a first voltage (e.g., a read voltage) during an activation phase of a read operation. After biasing the memory cell to the first voltage, the memory device may bias the memory cell to a second voltage greater than the first voltage (e.g., a write voltage) during the activation phase of the read operation. After biasing the memory cell to the second voltage, the memory device may initiate a refresh phase of the read operation. Based on a value stored by the memory cell prior to biasing the memory cell to the first voltage, the memory device may initiate a precharge phase of the read operation.

    Ferroelectric memory cell recovery
    5.
    发明授权
    Ferroelectric memory cell recovery 有权

    公开(公告)号：US10410737B2

    公开(公告)日：2019-09-10

    申请号：US16392015

    申请日：2019-04-23

    Applicant: Micron Technology, Inc.

    Inventor： Marcello Mariani ,  Giorgio Servalli ,  Andrea Locatelli

    IPC: G11C11/22 ,  G11C29/50

    Abstract: Methods, systems, and devices for recovering fatigued ferroelectric memory cells are described. Recovery voltages may be applied to a ferroelectric memory cell that is fatigued due to repeated access (read or write) operations. The recovery voltage may have a greater amplitude than the access voltage and may include multiple voltage pulses or a constant voltage. The recovery operation may be performed in the background as the memory array operates, or it may be performed when a host device is not actively using the memory array. The recovery operations may be performed periodically or may include discrete series of pulses distributed among several instances.

    Digit line voltage boosting systems and methods
    6.
    发明授权
    Digit line voltage boosting systems and methods 有权

    公开(公告)号：US12094512B2

    公开(公告)日：2024-09-17

    申请号：US17896345

    申请日：2022-08-26

    Applicant: Micron Technology, Inc.

    Inventor： Angelo Visconti ,  Andrea Locatelli

    IPC: G11C11/22

    CPC classification number: G11C11/2295 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2293 ,  G11C11/2297

    Abstract: Systems and methods described herein may enable a memory system to selectively provide a signal boost to a memory cell in response to a change in operating condition, like a change in temperature. The systems and methods may include determining to generate a signal boost for a first duration of time and in response to determining to generate the signal boost, generating the signal boost causing an increase in voltage applied to a signal line coupled to a memory cell. The systems and methods may further include, after the first duration of time, ceasing generation of the signal boost.

    MEMORY CELL BIASING TECHNIQUES DURING A READ OPERATION
    8.
    发明申请
    MEMORY CELL BIASING TECHNIQUES DURING A READ OPERATION 有权

    公开(公告)号：US20220270667A1

    公开(公告)日：2022-08-25

    申请号：US17741136

    申请日：2022-05-10

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Locatelli ,  Giorgio Servalli ,  Angelo Visconti

    IPC: G11C11/4096 ,  G11C11/22 ,  G11C11/4097 ,  G11C11/406 ,  G11C11/4091

    Abstract: Methods, systems, and devices for biasing a memory cell during a read operation are described. For example, a memory device may bias a memory cell to a first voltage (e.g., a read voltage) during an activation phase of a read operation. After biasing the memory cell to the first voltage, the memory device may bias the memory cell to a second voltage greater than the first voltage (e.g., a write voltage) during the activation phase of the read operation. After biasing the memory cell to the second voltage, the memory device may initiate a refresh phase of the read operation. Based on a value stored by the memory cell prior to biasing the memory cell to the first voltage, the memory device may initiate a precharge phase of the read operation.

    Open page biasing techniques
    9.
    发明授权
    Open page biasing techniques 有权

    公开(公告)号：US10896712B2

    公开(公告)日：2021-01-19

    申请号：US16441806

    申请日：2019-06-14

    Applicant: Micron Technology, Inc.

    Inventor： Angelo Visconti ,  Andrea Locatelli ,  Giorgio Servalli

    IPC: G11C11/22 ,  G06F3/06

    Abstract: Methods, systems, and devices for biasing techniques, such as open page biasing techniques, are described. A memory cell may be accessed during an access phase of an access operation, for example, an open page access operation. An activate pulse may be applied to the memory cell during the access phase. The memory cell may be biased to a non-zero voltage after applying the activate pulse and before a pre-charge phase. The pre-charge phase of the access phase may be initiated after biasing the memory cell to the non-zero voltage.

    Ferroelectric memory cell recovery
    10.
    发明授权
    Ferroelectric memory cell recovery 有权

    公开(公告)号：US10304558B2

    公开(公告)日：2019-05-28

    申请号：US16181125

    申请日：2018-11-05

    Applicant: Micron Technology, Inc.

    Inventor： Marcello Mariani ,  Giorgio Servalli ,  Andrea Locatelli

    IPC: G11C11/22 ,  G11C29/50

    Abstract: Methods, systems, and devices for recovering fatigued ferroelectric memory cells are described. Recovery voltages may be applied to a ferroelectric memory cell that is fatigued due to repeated access (read or write) operations. The recovery voltage may have a greater amplitude than the access voltage and may include multiple voltage pulses or a constant voltage. The recovery operation may be performed in the background as the memory array operates, or it may be performed when a host device is not actively using the memory array. The recovery operations may be performed periodically or may include discrete series of pulses distributed among several instances.

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