Invention Application
- Patent Title: Programmable logic arrays
- Patent Title (中): 可编程逻辑阵列
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Application No.: US09782173Application Date: 2001-02-12
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Publication No.: US20010030554A1Publication Date: 2001-10-18
- Inventor: Stefano Ghezzi , Donato Ferrario , Emilio Yero , Giovanni Campardo
- Applicant: STMicroelectronics S.r.l.
- Applicant Address: IT Agrate Brianza
- Assignee: STMicroelectronics S.r.l.
- Current Assignee: STMicroelectronics S.r.l.
- Current Assignee Address: IT Agrate Brianza
- Priority: EP00830102.0 20000214
- Main IPC: H03K019/177
- IPC: H03K019/177

Abstract:
A programmable logic array (PLA) includes at least one AND plane including an array of transistors arranged in rows and columns. The transistors belonging to a same column may be connected in series with each other. Two end conduction terminals of the series connected transistors may be coupled to a supply voltage rail and to a reference, respectively. The transistors of the first and last rows of the array may have their control terminals coupled to respective opposite enabling/disabling potentials. Except for the first and last rows, first, second, and third control lines are associated with each row of the array. Except for the first and last rows, each transistor of each row may have its control terminal connected to one of the three control lines associated with its row. The PLA may alternatively include at least one OR plane.
Public/Granted literature
- US06396168B2 Programmable logic arrays Public/Granted day:2002-05-28
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