公开(公告)号：US20010030554A1

公开(公告)日：2001-10-18

申请号：US09782173

申请日：2001-02-12

Applicant: STMicroelectronics S.r.l.

Inventor： Stefano Ghezzi ,  Donato Ferrario ,  Emilio Yero ,  Giovanni Campardo

IPC: H03K019/177

CPC classification number: H03K19/17736 ,  H03K19/17704 ,  H03K19/1778 ,  Y10T307/505

Abstract: A programmable logic array (PLA) includes at least one AND plane including an array of transistors arranged in rows and columns. The transistors belonging to a same column may be connected in series with each other. Two end conduction terminals of the series connected transistors may be coupled to a supply voltage rail and to a reference, respectively. The transistors of the first and last rows of the array may have their control terminals coupled to respective opposite enabling/disabling potentials. Except for the first and last rows, first, second, and third control lines are associated with each row of the array. Except for the first and last rows, each transistor of each row may have its control terminal connected to one of the three control lines associated with its row. The PLA may alternatively include at least one OR plane.

Abstract translation: 可编程逻辑阵列（PLA）包括至少一个AND平面，其包括以行和列排列的晶体管阵列。 属于同一列的晶体管可以彼此串联连接。 串联连接的晶体管的两个端部导电端子可以分别耦合到电源电压轨和参考。 阵列的第一行和最后一行的晶体管可以使它们的控制端耦合到各自相对的使能/禁止电位。 除了第一行和最后一行，第一，第二和第三控制行都与数组的每一行相关联。 除了第一行和最后一行之外，每行的每个晶体管可以将其控制端连接到与其行相关联的三条控制线之一。 PLA可以替代地包括至少一个OR平面。