公开(公告)号：US20040205314A1

公开(公告)日：2004-10-14

申请号：US10781974

申请日：2004-02-18

Applicant: STMicroelectronics S.r.l.

Inventor： Irene Babudri ,  Stefano Ghezzi ,  Giuseppe Giannini ,  Ruggero DeLuca

IPC: G06F012/14

CPC classification number: G06F12/1425

Abstract: A memory, particularly but not limitatively a flash memory, comprises at least one data storage area comprising a plurality of data storage locations, and an access circuitry for accessing the data storage locations for either retrieving or altering a data content thereof, depending for example on a memory user request. The memory includes at least one first user-configurable flag element and a second user-configurable flag element. Both the at least one first and the second flag elements are used by a user to set a protected state of the respective data storage area against alteration of the content of the data storage locations thereof. The protected state defined by setting the first flag element is user-removable, i.e., it can be removed by request from the user, so as to enable again the alteration of the content of the data storage area. On the contrary, the protected state defined by setting the second flag element is permanent and, once set, it cannot be removed: the data storage area becomes unalterable.

Abstract translation: 存储器，特别地但不限于闪速存储器，包括至少一个包括多个数据存储位置的数据存储区域，以及用于访问数据存储位置以用于检索或更改其数据内容的访问电路，这取决于例如 内存用户请求。 存储器包括至少一个第一用户可配置标志元件和第二用户可配置标志元件。 所述至少一个第一和第二标志元素都由用户用于设置相应数据存储区域的受保护状态以防其数据存储位置的内容的改变。 通过设置第一标志元素定义的受保护状态是用户可移除的，即，可以通过来自用户的请求去除它，以便再次启用数据存储区域的内容的改变。 相反，通过设置第二标志元素定义的受保护状态是永久性的，一旦设置，就不能被去除：数据存储区域变得不可更改。

公开(公告)号：US20010030554A1

公开(公告)日：2001-10-18

申请号：US09782173

申请日：2001-02-12

Applicant: STMicroelectronics S.r.l.

Inventor： Stefano Ghezzi ,  Donato Ferrario ,  Emilio Yero ,  Giovanni Campardo

IPC: H03K019/177

CPC classification number: H03K19/17736 ,  H03K19/17704 ,  H03K19/1778 ,  Y10T307/505

Abstract: A programmable logic array (PLA) includes at least one AND plane including an array of transistors arranged in rows and columns. The transistors belonging to a same column may be connected in series with each other. Two end conduction terminals of the series connected transistors may be coupled to a supply voltage rail and to a reference, respectively. The transistors of the first and last rows of the array may have their control terminals coupled to respective opposite enabling/disabling potentials. Except for the first and last rows, first, second, and third control lines are associated with each row of the array. Except for the first and last rows, each transistor of each row may have its control terminal connected to one of the three control lines associated with its row. The PLA may alternatively include at least one OR plane.

Abstract translation: 可编程逻辑阵列（PLA）包括至少一个AND平面，其包括以行和列排列的晶体管阵列。 属于同一列的晶体管可以彼此串联连接。 串联连接的晶体管的两个端部导电端子可以分别耦合到电源电压轨和参考。 阵列的第一行和最后一行的晶体管可以使它们的控制端耦合到各自相对的使能/禁止电位。 除了第一行和最后一行，第一，第二和第三控制行都与数组的每一行相关联。 除了第一行和最后一行之外，每行的每个晶体管可以将其控制端连接到与其行相关联的三条控制线之一。 PLA可以替代地包括至少一个OR平面。