Invention Application
- Patent Title: Low jitter external clocking
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Application No.: US10132599Application Date: 2002-04-25
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Publication No.: US20020125930A1Publication Date: 2002-09-12
- Inventor: Rajendran Nair , Gregory E. Dermer , Stephen R. Mooney , Nitin Y. Borkar
- Applicant: Intel Corporation
- Applicant Address: null
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: null
- Main IPC: G06F001/04
- IPC: G06F001/04

Abstract:
A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.
Public/Granted literature
- US06798265B2 Low jitter external clocking Public/Granted day:2004-09-28
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