公开(公告)号：US20020125930A1

公开(公告)日：2002-09-12

申请号：US10132599

申请日：2002-04-25

Applicant: Intel Corporation

Inventor： Rajendran Nair ,  Gregory E. Dermer ,  Stephen R. Mooney ,  Nitin Y. Borkar

IPC: G06F001/04

CPC classification number: G06F1/10 ,  H03K5/2481

Abstract: A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.