公开(公告)号：US20020070777A1

公开(公告)日：2002-06-13

申请号：US09735858

申请日：2000-12-13

Applicant: Intel Corporation

Inventor： Michael Pang-Cheng Hsu ,  Rajendran Nair ,  Stephen R. Mooney

IPC: H03D001/00

CPC classification number: H03F3/45219 ,  H03D13/003 ,  H03F3/45183 ,  H03F2203/45318 ,  H03F2203/45394 ,  H03F2203/45674 ,  H03L7/091

Abstract: A voltage-to-current circuit utilizes an NMOS-input voltage-to-current (V-I) converter and a PMOS-input V-I converter, with both driving a common gate output stage. Each of the V-I converters includes a transconductance amplifier and a current mirror. The common gate output stage includes two series connected complementary pairs of transistors. One complementary pair drives the output, and the other complementary pair biases the first. The V-I circuit can be utilized as part of a phase detector, which is in turn can be utilized as part of a phase lock loop or a delay lock loop.

Abstract translation: 电压 - 电流电路使用NMOS输入电压 - 电流（V-I）转换器和PMOS输入V-I转换器，同时驱动公共栅极输出级。 每个V-I转换器包括跨导放大器和电流镜。 公共栅极输出级包括两个串联的互补晶体管对。 一对互补对驱动输出，另一个互补对偏置第一个。 V-I电路可以用作相位检测器的一部分，相位检测器又可以用作锁相环或延迟锁定环路的一部分。

公开(公告)号：US20040169536A1

公开(公告)日：2004-09-02

申请号：US10797508

申请日：2004-03-10

Applicant: Intel Corporation

Inventor： Michael Pang-Cheng Hsu ,  Rajendran Nair ,  Stephen R. Mooney

IPC: H03L007/06

CPC classification number: H03F3/45219 ,  H03D13/003 ,  H03F3/45183 ,  H03F2203/45318 ,  H03F2203/45394 ,  H03F2203/45674 ,  H03L7/091

Abstract: A variety of embodiments may include a voltage controlled oscillator to generate a differential signal on two nodes; and phase detector to compare a phase of the differential signal and a phase of a received signal, the phase detector including a sampling circuit to periodically sample voltage values on the two nodes, and a linear voltage-to-current converter responsive to the voltage values to create a control voltage for the voltage controlled oscillator.

Abstract translation: 各种实施例可以包括压控振荡器以在两个节点上产生差分信号; 和相位检测器，用于比较差分信号的相位和接收信号的相位，所述相位检测器包括采样电路，以周期性地对两个节点上的电压值进行采样;以及响应于电压值的线性电压 - 电流转换器 以创建压控振荡器的控制电压。

公开(公告)号：US20020125930A1

公开(公告)日：2002-09-12

申请号：US10132599

申请日：2002-04-25

Applicant: Intel Corporation

Inventor： Rajendran Nair ,  Gregory E. Dermer ,  Stephen R. Mooney ,  Nitin Y. Borkar

IPC: G06F001/04

CPC classification number: G06F1/10 ,  H03K5/2481

Abstract: A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.

公开(公告)号：US20040188811A1

公开(公告)日：2004-09-30

申请号：US10396945

申请日：2003-03-24

Applicant: Intel Corporation

Inventor： Gilroy J. Vandentop ,  Rajendran Nair

IPC: H01L021/44

CPC classification number: H01L25/18 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2224/0401

Abstract: An apparatus and system, as well as methods for providing them, may include a die having a core circuit electrically coupled to a power converter included in an active substrate.

Abstract translation: 装置和系统以及用于提供它们的方法可以包括具有电耦合到包括在有源基板中的功率转换器的核心电路的管芯。

公开(公告)号：US20030021143A1

公开(公告)日：2003-01-30

申请号：US09912634

申请日：2001-07-24

Applicant: Intel Corporation

Inventor： Rajendran Nair

IPC: G11C011/22

CPC classification number: G11C11/22

Abstract: A ferroelectric memory device and method for reading such a device utilize an AC excitation on an active bit line to cancel sneak currents during a read operation. A memory device comprises an active ferroelectric cell disposed between an active word line and an active bit line, and a passive ferroelectric cell disposed between a passive word line and the active bit line. Peripheral circuitry is adapted to drive the active word line with active word line biasing, the passive word line with passive word line biasing, and the active bit line with an AC excitation during a read operation.

Abstract translation: 用于读取这种器件的铁电存储器件和方法利用有源位线上的AC激励来在读取操作期间消除潜行电流。 存储器件包括位于有源字线和有源位线之间的有源铁电单元，以及设置在无源字线和有源位线之间的被动铁电单元。 外设电路适用于通过有源字线偏置驱动有源字线，无源字线偏置的被动字线以及在读操作期间具有AC激励的有源位线。

公开(公告)号：US20020149432A1

公开(公告)日：2002-10-17

申请号：US10146689

申请日：2002-05-14

Applicant: Intel Corporation

Inventor： Michael Pang-Cheng Hsu ,  Rajendran Nair ,  Stephen R. Mooney

IPC: H03L007/00

CPC classification number: H03F3/45219 ,  H03D13/003 ,  H03F3/45183 ,  H03F2203/45318 ,  H03F2203/45394 ,  H03F2203/45674 ,  H03L7/091

Abstract: A voltage-to-current circuit utilizes an NMOS-input voltage-to-current (V-I) converter and a PMOS-input V-I converter, with both driving a common gate output stage. Each of the V-I converters includes a transconductance amplifier and a current mirror. The common gate output stage includes two series connected complementary pairs of transistors. One complementary pair drives the output, and the other complementary pair biases the first. The V-I circuit can be utilized as part of a phase detector, which is in turn can be utilized as part of a phase lock loop or a delay lock loop.