Process for manufacturing an isolated-gate transistor with an architecture of the substrate-on-insulator type, and corresponding transistor

Invention Application

US20020135020A1 Process for manufacturing an isolated-gate transistor with an architecture of the substrate-on-insulator type, and corresponding transistor 有权

Title translation: 用于制造具有绝缘体基板类型的结构的隔离栅晶体管的工艺以及相应的晶体管

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Patent Title: Process for manufacturing an isolated-gate transistor with an architecture of the substrate-on-insulator type, and corresponding transistor
Patent Title (中): 用于制造具有绝缘体基板类型的结构的隔离栅晶体管的工艺以及相应的晶体管
Application No.: US10084255

Application Date: 2002-02-27
Publication No.: US20020135020A1

Publication Date: 2002-09-26
Inventor: Thomas Skotnicki , Stephane Monfray , Alexandre Villaret
Applicant: STMicroelectronics S.A.
Applicant Address: FR Montrouge
Assignee: STMicroelectronics S.A.
Current Assignee: STMicroelectronics S.A.
Current Assignee Address: FR Montrouge
Priority: FR0102745 20010228
Main IPC: H01L029/76
IPC: H01L029/76 ; H01L029/94 ; H01L031/062 ; H01L031/113

Process for manufacturing an isolated-gate transistor with an architecture of the substrate-on-insulator type, and corresponding transistor

Abstract:

The source, drain and channel regions are produced in a silicon layer completely isolated vertically from a carrier substrate by an insulating layer, and are bounded laterally by a lateral isolation region of the shallow trench type.

Abstract(Chinese):

源极，漏极和沟道区域通过绝缘层在垂直于载体衬底完全隔离的硅层中产生，并且通过浅沟槽类型的横向隔离区域横向限定。

Public/Granted literature

US06656782B2 Process for manufacturing an isolated-gate transistor with an architecture of the substrate-on-insulator type, and corresponding transistor Public/Granted day:2003-12-02

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