公开(公告)号：US20030038315A1

公开(公告)日：2003-02-27

申请号：US10273925

申请日：2002-10-18

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Didier Dutartre ,  Pascal Ribot ,  Maryse Paoli ,  Richard Fournel

IPC: H01L021/336 ,  H01L029/788

CPC classification number: H01L29/66825 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42336

Abstract: A non-volatile memory includes a floating gate extending in a substrate between source and drain regions. A channel region may be confined by two insulating layers. The invention is particularly applicable to EPROM, EEPROM, Flash and single-electron memories using CMOS technology.

Abstract translation: 非易失性存储器包括在源极和漏极区域之间的衬底中延伸的浮动栅极。 通道区域可以被两个绝缘层限制。 本发明特别适用于使用CMOS技术的EPROM，EEPROM，闪存和单电子存储器。

公开(公告)号：US20040016968A1

公开(公告)日：2004-01-29

申请号：US10409653

申请日：2003-04-08

Applicant: STMICROELECTRONICS S.A.

Inventor： Philippe Coronel ,  Stephane Monfray ,  Thomas Skotnicki

IPC: H01L021/84 ,  H01L031/0392

CPC classification number: H01L29/66772 ,  H01L29/78648 ,  H01L29/78654

Abstract: A semiconductor device is provided that includes a semiconductor channel region extending above a semiconductor substrate in a longitudinal direction between a semiconductor source region and a semiconductor drain region, and a gate region extending in the transverse direction, coating the channel region, and insulated from the channel region. The source, channel, and drain regions are formed in a continuous semiconductor layer that is approximately plane and parallel to the upper surface of the substrate. Additionally, the source, drain, and gate regions are coated in an insulating coating so as to provide electrical insulation between the gate region and the source and drain regions, and between the substrate and the source, drain, gate, and channel regions. Also provided is an integrated circuit that includes such a semiconductor device, and a method for manufacturing such a semiconductor device.

Abstract translation: 提供一种半导体器件，其包括在半导体源极区域和半导体漏极区域之间沿纵向方向在半导体衬底上方延伸的半导体沟道区域和在横向方向上延伸的栅极区域，涂覆沟道区域并与 渠道区域。 源极，沟道和漏极区域形成在大致平面并平行于衬底的上表面的连续半导体层中。 此外，源极，漏极和栅极区域被涂覆在绝缘涂层中，以便在栅极区域和源极和漏极区域之间以及衬底与源极，漏极，栅极和沟道区域之间提供电绝缘。 还提供了一种包括这种半导体器件的集成电路及其制造方法。

公开(公告)号：US20020135020A1

公开(公告)日：2002-09-26

申请号：US10084255

申请日：2002-02-27

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Stephane Monfray ,  Alexandre Villaret

IPC: H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/113

CPC classification number: H01L29/66651 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/76281 ,  H01L21/76289 ,  H01L29/66772

Abstract: The source, drain and channel regions are produced in a silicon layer completely isolated vertically from a carrier substrate by an insulating layer, and are bounded laterally by a lateral isolation region of the shallow trench type.

Abstract translation: 源极，漏极和沟道区域通过绝缘层在垂直于载体衬底完全隔离的硅层中产生，并且通过浅沟槽类型的横向隔离区域横向限定。

公开(公告)号：US20010005618A1

公开(公告)日：2001-06-28

申请号：US09738870

申请日：2000-12-15

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Malgorzata Jurczak ,  Didier Dutartre

IPC: H01L021/00 ,  H01L021/84 ,  C30B001/00 ,  H01L021/20 ,  H01L021/36

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/76262 ,  H01L29/0673 ,  H01L29/0676

Abstract: The process for fabricating a network of nanometric lines made of single-crystal silicon on an isolating substrate includes the production of a substrate comprising a silicon body having a lateral isolation defining a central part in the body. A recess is formed in the central part having a bottom wall made of dielectric material, a first pair of opposed parallel sidewalls made of dielectric material, and a second pair of opposed parallel sidewalls. At least one of the opposed parallel sidewalls of the second pair being formed from single-crystal silicon. The method further includes the epitaxial growth in the recess, from the sidewall made of single-crystal silicon of the recess, of an alternating network of parallel lines made of single-crystal SiGe alloy and of single-crystal silicon. Also, the lines made of single-crystal SiGe alloy are etched to form in the recess a network of parallel lines made of single-crystal silicon insulated from each other.

Abstract translation: 用于在隔离衬底上制造由单晶硅制成的纳米线网络的工艺包括制备包含限定主体中心部分的侧向隔离的硅体的衬底。 在具有由电介质材料制成的底壁的中心部分形成凹部，由电介质材料制成的第一对相对的平行侧壁和第二对相对的平行侧壁。 第二对的相对的平行侧壁中的至少一个由单晶硅形成。 该方法还包括从由凹槽的单晶硅制成的侧壁，由单晶SiGe合金和单晶硅制成的平行线的交替网络的凹槽中的外延生长。 此外，由单晶SiGe合金制成的线被蚀刻以在凹槽中形成由彼此绝缘的单晶硅硅制成的平行线的网络。

公开(公告)号：US20040033676A1

公开(公告)日：2004-02-19

申请号：US10421368

申请日：2003-04-23

Applicant: STMICROELECTRONICS S.A.

Inventor： Philippe Coronel ,  Francois Leverd ,  Thomas Skotnicki

IPC: H01L021/20 ,  H01L021/36

CPC classification number: H01L21/6835 ,  H01L21/32134 ,  H01L21/76251 ,  H01L23/544 ,  H01L27/10852 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/66484 ,  H01L29/66772 ,  H01L29/7831 ,  H01L29/78645 ,  H01L29/78648 ,  H01L51/0013 ,  H01L2221/68363 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/83894 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/00

Abstract: A method is provided for fabricating integrated electronic components. According to the method, an initial structure is produced on the surface of a first substrate. This initial structure incorporates a defined pattern formed from volumes of differentiated materials. At least part of the initial substrate that includes the defined pattern is transferred onto a second substrate, preferably by inverting the first substrate against the second substrate and then removing the first substrate. An additional structure is then produced on the second substrate. This additional structure includes volumes of material placed in correspondence with some of the volumes of differentiated material of the defined pattern. The electronic components thus produced may have a suitable configuration in accordance with technological or geometrical constraints. In a preferred method, a selective treatment is applied to the transferred part of the initial structure, so as to make a distinction between the volumes of differentiated material of the pattern.

Abstract translation: 提供了一种用于制造集成电子部件的方法。 根据该方法，在第一基板的表面上产生初始结构。 该初始结构包含由差异化材料体积形成的限定图案。 包括限定图案的初始衬底的至少一部分被转移到第二衬底上，优选地通过使第一衬底相对于第二衬底反转，然后去除第一衬底。 然后在第二基板上产生另外的结构。 该附加结构包括与限定图案的一些体积不同的材料相对应放置的材料体积。 如此生产的电子部件可以根据技术或几何约束具有合适的构造。 在优选的方法中，对初始结构的转移部分应用选择性处理，以区分图案的差异材料的体积。

公开(公告)号：US20020163027A1

公开(公告)日：2002-11-07

申请号：US10114672

申请日：2002-04-02

Applicant: STMICROELECTRONICS S.A.

Inventor： Thomas Skotnicki ,  Emmanuel Josse

IPC: H01L027/108

CPC classification number: H01L29/66666 ,  H01L29/165 ,  H01L29/7827

Abstract: The vertical insulated gate transistor includes, on a semiconductor substrate, a vertical pillar incorporating one of the source and drain regions at the top, a gate dielectric layer situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The other of the source and drain regions is in the bottom part of the pillar PIL and the insulated gate includes an isolated external portion 15 resting on the flanks of the pillar and an isolated internal portion 14 situated inside the pillar between the source and drain regions. The isolated internal portion is separated laterally from the isolated external portion by two connecting semiconductor regions PL1, PL2 extending between the source and drain regions, and forming two very fine pillars.

Abstract translation: 垂直绝缘栅晶体管包括在半导体衬底上的垂直柱，其顶部包括源极和漏极区中的一个，位于柱的侧面和衬底顶表面上的栅极电介质层，以及半导体 门静置在栅介质层上。 源极和漏极区域中的另一个位于柱PIL的底部，并且绝缘栅极包括搁置在柱的侧面上的隔离的外部部分15和位于源极和漏极区域之间的柱内的隔离的内部部分14 。 隔离的内部部分通过在源极和漏极区域之间延伸的两个连接半导体区域PL1，PL2从隔离的外部部分侧向分离，并形成两个非常细的柱。

公开(公告)号：US20020090781A1

公开(公告)日：2002-07-11

申请号：US10042506

申请日：2002-01-08

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Stephane Monfray ,  Catherine Mallardeau

IPC: H01L021/8242

CPC classification number: H01L27/1087 ,  H01L27/10832

Abstract: A process for making a DRAM-type cell includes growing layers of silicon germanium and layers of silicon, by epitaxy from a silicon substrate; superposing a first layer of Nnull doped silicon and a second layer of P doped silicon; and forming a transistor on the silicon substrate. The method also includes etching a trench in the extension of the transistor to provide an access to the silicon germanium layers relative to the silicon layers over a pre-set depth to form lateral cavities, and forming a capacitor in the trench and in the lateral cavities.

Abstract translation: 通过从硅衬底外延生长制造DRAM型电池的工艺包括生长硅锗层和硅层; 叠加第一层N +掺杂硅和第二层P掺杂硅; 以及在硅衬底上形成晶体管。 该方法还包括蚀刻晶体管的延伸中的沟槽，以提供在预定深度上相对于硅层访问硅锗层以形成横向空腔，以及在沟槽和侧向空腔中形成电容器 。

公开(公告)号：US20040262690A1

公开(公告)日：2004-12-30

申请号：US10817147

申请日：2004-04-02

Applicant: STMicroelectronics S.A.

Inventor： Philippe Coronel ,  Yves Morand ,  Thomas Skotnicki ,  Robin Cerutti

IPC: H01L027/148 ,  H01L029/768 ,  H01L029/76 ,  H01L021/336

CPC classification number: H01L29/78696 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/78645 ,  H01L29/78648

Abstract: A MOS transistor formed in a silicon substrate comprising an active area surrounded with an insulating wall, a first conductive strip covering a central strip of the active area, one or several second conductive strips placed in the active area right above the first strip, and conductive regions placed in two recesses of the insulating wall and placed against the ends of the first and second strips, the silicon surfaces opposite to the conductive strips and regions being covered with an insulator forming a gate oxide.

Abstract translation: 一种形成在硅衬底中的MOS晶体管，包括被绝缘壁包围的有源区域，覆盖有源区域的中心条带的第一导电条，放置在位于第一条带正上方的有源区域中的一个或多个第二导电条，以及导电 放置在绝缘壁的两个凹部中并且抵靠第一和第二条带的端部放置的区域，与导电条带和区域相对的硅表面被形成栅极氧化物的绝缘体覆盖。

公开(公告)号：US20040150024A1

公开(公告)日：2004-08-05

申请号：US10702066

申请日：2003-11-05

Applicant: STMICROELECTRONICS S.A.

Inventor： Pascale Mazoyer ,  Alexandre Villaret ,  Thomas Skotnicki

IPC: H01L027/108

CPC classification number: B82Y10/00 ,  G11C2216/08 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7888

Abstract: An integrated memory circuit includes at least one memory cell formed by a single transistor whose gate (GR) has a lower face insulated from a channel region by an insulation layer containing a succession of potential wells, which are substantially arranged at a distance from the gate and from the channel region in a plane substantially parallel to the lower face of the gate. The potential wells are capable of containing an electric charge which is confined in the plane and can be controlled to move in the plane towards a first confinement region next to the source region or towards a second confinement region next to the drain region so as to define two memory states for the cell.

Abstract translation: 集成存储器电路包括由单个晶体管形成的至少一个存储单元，其栅极（GR）具有通过包含一系列势阱的绝缘层与沟道区域绝缘的下表面，绝缘层基本上布置在与栅极相距一定距离处 并且在基本上平行于栅极的下表面的平面中的沟道区域中。 势阱能够容纳限制在平面中的电荷，并且可以控制其在平面内朝向源极区域旁边的第一限制区域或靠近漏极区域的第二限制区域移动，以便限定 两个单元的内存状态。

公开(公告)号：US20020076899A1

公开(公告)日：2002-06-20

申请号：US09920315

申请日：2001-08-01

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Michel Haond ,  Didier Dutartre

IPC: H01L021/76

CPC classification number: H01L21/76264 ,  H01L21/76283

Abstract: Processes are provided for fabricating a substrate having a silicon-on-insulator (SOI) or silicon-on-nothing (SON) architecture, which are applicable to the manufacture of semiconductor devices, especially transistors such as those of the MOS, CMOS, BICMOS, and HCMOS types. In the fabrication processes, a multilayer stack is grown on a substrate by non-selective full-wafer epitaxy. The multilayer stack includes a silicon layer on a Ge or SiGe layer. Active regions are defined and masked, and insulating pads are formed so as to be located around the perimeter of each of the active regions at predetermined intervals and placed against the sidewalls of the active regions. The insulating trenches are etched, and the SiGe or Ge layer is laterally etched so as to form an empty tunnel under the silicon layer. The trenches are filled with a dielectric. In the case of an SOI archiutecture, the tunnel is filled with a dielectric.

Abstract translation: 提供了用于制造具有绝缘体上硅（SOI）或无硅（SON）结构的衬底的工艺，其可应用于半导体器件的制造，特别是诸如MOS，CMOS，BICMOS的晶体管 和HCMOS类型。 在制造工艺中，通过非选择性全晶片外延在衬底上生长多层叠层。 多层堆叠包括Ge或SiGe层上的硅层。 有源区被限定和掩蔽，并且绝缘垫被形成为以预定的间隔围绕每个有源区的周边定位并且抵靠有源区的侧壁放置。 绝缘沟槽被蚀刻，SiGe或Ge层被横向蚀刻，以便在硅层下方形成一个空洞。 沟槽填充有电介质。 在SOI结构的情况下，隧道填充有电介质。