Invention Application
- Patent Title: Vertical electronic circuit package and method of fabrication therefor
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Application No.: US10371659Application Date: 2003-02-21
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Publication No.: US20030151146A1Publication Date: 2003-08-14
- Inventor: Chee-Yee Chung , David G. Figueroa , Robert L. Sankman
- Applicant: Intel Corporation
- Applicant Address: null
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: null
- Main IPC: H01L023/48
- IPC: H01L023/48

Abstract:
An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.
Public/Granted literature
- US06680218B2 Fabrication method for vertical electronic circuit package and system Public/Granted day:2004-01-20
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