公开(公告)号：US20040118594A1

公开(公告)日：2004-06-24

申请号：US10323165

申请日：2002-12-18

Applicant: Intel Corporation

Inventor： Thomas S. Dory ,  Michael Walk ,  Robert L. Sankman ,  Boyd L. Coomer

IPC: H05K003/20 ,  H05K001/11

CPC classification number: H05K3/107 ,  H05K3/0014 ,  H05K3/005 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/1189 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: To decrease the complexity, time, and cost of fabricating an electronics package, and to potentially increase the quality and decrease the size thereof, the package includes at least one electronic component mounted on an imprinted substrate. In an embodiment, the substrate may comprise conductive traces, vias, and patterns of lands on one or more layers. Such features may be formed by imprinting in one operation rather than sequentially. Conductor features, such as trenches, holes, and planes, may be formed of different sizes simultaneously. Methods of fabrication, as well as application of the imprinted package to an electronic assembly, are also described.

Abstract translation: 为了降低制造电子封装的复杂性，时间和成本，并且潜在地提高质量并减小其尺寸，封装包括安装在压印基板上的至少一个电子部件。 在一个实施例中，衬底可以包括导电迹线，通路和一个或多个层上的焊盘图案。 这些特征可以通过在一个操作中打印而不是顺序地形成。 诸如沟槽，孔和平面的导体特征可以同时由不同尺寸形成。 还描述了制造方法以及将印刷包装应用于电子组件。

公开(公告)号：US20030151146A1

公开(公告)日：2003-08-14

申请号：US10371659

申请日：2003-02-21

Applicant: Intel Corporation

Inventor： Chee-Yee Chung ,  David G. Figueroa ,  Robert L. Sankman

IPC: H01L023/48

CPC classification number: H05K1/141 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K1/0298 ,  H05K3/3436 ,  H05K3/366 ,  H05K2201/0919 ,  H05K2201/10446 ,  H05K2201/10454 ,  H05K2201/10674 ,  H05K2201/10719 ,  H01L2224/05599

Abstract: An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.

公开(公告)号：US20030072140A1

公开(公告)日：2003-04-17

申请号：US09977124

申请日：2001-10-12

Applicant: Intel Corporation

Inventor： Chee-Yee Chung ,  Robert L. Sankman ,  Alex Waizman

IPC: H05K007/06 ,  H05K003/30

CPC classification number: H05K1/167 ,  H01L23/50 ,  H01L23/647 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/095 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/0317 ,  H05K2201/09309 ,  H05K2201/0949 ,  H05K2201/0979 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A resistive element, a circuit board, and a circuit package, as well as a method of adding a resistive element to a circuit board are described. The resistive element includes a first contact point connected to a capacitor terminal, a second contact point connected to a circuit board plane, and resistive material connected to the first and second contact points. The invention may also include a circuit board with one or more resistive elements, as well as a circuit package, such as an integrated circuit or a discrete bypass capacitor, including one or more resistive elements, applied to an outside surface. The value of resistance for the resistive element can be selected by design to have a predetermined relationship with the equivalent resistance of an associated circuit board and connecting circuitry.

Abstract translation: 描述了电阻元件，电路板和电路封装以及将电阻元件添加到电路板的方法。 电阻元件包括连接到电容器端子的第一接触点，连接到电路板平面的第二接触点和连接到第一和第二接触点的电阻材料。 本发明还可以包括具有一个或多个电阻元件的电路板，以及包括施加到外表面的一个或多个电阻元件的电路封装，例如集成电路或分立旁路电容器。 可以通过设计来选择电阻元件的电阻值以与相关联的电路板和连接电路的等效电阻具有预定的关系。

公开(公告)号：US20040173901A1

公开(公告)日：2004-09-09

申请号：US10382680

申请日：2003-03-05

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Robert L. Sankman

IPC: H01L023/48

CPC classification number: H05K1/0204 ,  H01L23/13 ,  H01L23/36 ,  H01L23/4006 ,  H01L23/49816 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H05K1/182 ,  H05K2201/09054 ,  H05K2201/1056 ,  H05K2201/10734 ,  Y10T29/49124 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A method and apparatus for making a package having improved heat conduction characteristics and high frequency response. A relatively thick package substrate, such as copper, has a wiring layer bonded to one face, leaving the opposite face exposed, for example, to be a surface for connection to a heat sink. One ore more chips are bonded to the wiring layer, and an array of connectors, such as solder balls are provided around the periphery of the chip(s) for connection to a printed circuit board. In some embodiments, the printed circuit board has a hole that the chip(s) extend into to allow smaller external-connection solder balls. In some embodiments, a second heat sink is connected to the back of the chip through the PCB hole.

Abstract translation: 一种用于制造具有改善的热传导特性和高频响应的封装的方法和装置。 诸如铜的相对厚的封装衬底具有结合到一个面的布线层，使相对的面露出，例如是用于连接到散热器的表面。 将一个或多个芯片接合到布线层，并且在芯片的周边周围设置连接器阵列（例如焊球），以连接到印刷电路板。 在一些实施例中，印刷电路板具有一个孔，芯片延伸进入以允许更小的外部连接焊球。 在一些实施例中，第二散热器通过PCB孔连接到芯片的背面。

公开(公告)号：US20030151147A1

公开(公告)日：2003-08-14

申请号：US10371827

申请日：2003-02-21

Applicant: Intel Corporation

Inventor： Chee-Yee Chung ,  David G. Figueroa ,  Robert L. Sankman

IPC: H01L023/48

CPC classification number: H05K1/141 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K1/0298 ,  H05K3/3436 ,  H05K3/366 ,  H05K2201/0919 ,  H05K2201/10446 ,  H05K2201/10454 ,  H05K2201/10674 ,  H05K2201/10719 ,  H01L2224/05599

Abstract: An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.

Abstract translation: 电子电路封装包括电连接到水平封装部分（图3的306）的垂直封装部分（304，图3）。 垂直封装部分包括与垂直平面平行取向的多个导电层（512,514,516，图5）。 垂直部分的水平顶面（图6中的608）上的第一组接合焊盘（606，图6）可以连接到集成电路（图6的302）的接合焊盘（602，图6）。 3）。 垂直部分的水平底面（图6中的614）上的第二组接合焊盘（612，图6））可以连接到水平封装部分上的接合焊盘（616，图6）。 垂直部分的导电层在第一方向上进行接合焊盘间距转换，并且水平封装部分内的导电结构（906,908,910，图9）在第二方向上执行接合焊盘间距转换。

公开(公告)号：US20030102555A1

公开(公告)日：2003-06-05

申请号：US10006292

申请日：2001-12-03

Applicant: Intel Corporation

Inventor： P. R. Patel ,  Chee-Yee Chung ,  Daivd G. Figueroa ,  Robert L. Sankman ,  Yuan-Liang Li ,  Hong Xie ,  William P. Pinello

IPC: H01L021/44 ,  H01L021/48 ,  H01L021/50 ,  H01L021/8234 ,  H01L023/34 ,  H01L023/24 ,  H01L023/22

CPC classification number: H01L24/81 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00

Abstract: To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Abstract translation: 为了提供高速，低电感电容去耦，集成电路（IC）封装包括位于管芯和IC封装衬底之间的安装区域内的电容器。 各种类型和尺寸的电容器和基板可以用于各种几何布置。 在一些实施例中，电容器夹在裸片端子或凸起之间以及衬底导体或衬垫之间，而在其它实施例中，电容器位于IC封装衬底的表面上的棒状导体之间。 还描述了制造方法以及将包装应用于电子组件和电子系统。

公开(公告)号：US20030003705A1

公开(公告)日：2003-01-02

申请号：US09897369

申请日：2001-07-02

Applicant: Intel Corporation

Inventor： Chee-Yee Chung ,  David G. Figueroa ,  Robert L. Sankman

IPC: H01L021/44

CPC classification number: H05K1/141 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K1/0298 ,  H05K3/3436 ,  H05K3/366 ,  H05K2201/0919 ,  H05K2201/10446 ,  H05K2201/10454 ,  H05K2201/10674 ,  H05K2201/10719 ,  H01L2224/05599

Abstract: An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.

Abstract translation: 电子电路封装包括电连接到水平封装部分（图3的306）的垂直封装部分（304，图3）。 垂直封装部分包括与垂直平面平行取向的多个导电层（512,514,516，图5）。 垂直部分的水平顶面（图6中的608）上的第一组接合焊盘（606，图6）可以连接到集成电路（图6的302）的接合焊盘（602，图6）。 3）。 垂直部分的水平底面（图6中的614）上的第二组接合焊盘（612，图6））可以连接到水平封装部分上的接合焊盘（616，图6）。 垂直部分的导电层在第一方向上进行接合焊盘间距转换，并且水平封装部分内的导电结构（906,908,910，图9）在第二方向上执行接合焊盘间距转换。

公开(公告)号：US20020172026A1

公开(公告)日：2002-11-21

申请号：US09858238

申请日：2001-05-15

Applicant: Intel Corporation

Inventor： Tee Onn Chong ,  Seng Hooi Ong ,  Robert L. Sankman

IPC: H05K007/06

CPC classification number: H05K1/114 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K2201/09227 ,  H05K2201/10674 ,  H05K2201/10734

Abstract: An electronics package comprises an integrated circuit (IC) coupled to an IC substrate in a flip-chip ball grid array (FCBGA) configuration. The IC comprises a high density pattern of interconnect pads around its periphery for coupling to a corresponding pattern of bonding pads on the IC substrate. The substrate bonding pads are uniquely arranged to accommodate a high density of interconnect pads on the IC while taking into account various geometrical constraints on the substrate, such as bonding pad size, trace width, and trace spacing. In one embodiment, the substrate bonding pads are arranged in a zigzag pattern. In a further embodiment, the technique is used for bonding pads on a printed circuit board to which an IC package is coupled. Methods of fabrication, as well as application of the package to an electronic package, an electronic system, and a data processing system, are also described.

Abstract translation: 电子封装包括以倒装芯片球栅阵列（FCBGA）配置耦合到IC基板的集成电路（IC）。 IC包括围绕其周边的互连焊盘的高密度图案，用于耦合到IC衬底上的对应图案的焊盘。 衬底接合焊盘被独特地布置成在IC上容纳高密度的互连焊盘，同时考虑到衬底上的各种几何约束，例如焊盘尺寸，迹线宽度和迹线间距。 在一个实施例中，衬底接合焊盘以锯齿形图案布置。 在另一实施例中，该技术用于将IC封装耦合到的印刷电路板上的焊盘接合。 还描述了制造方法以及将包装应用于电子包装，电子系统和数据处理系统。