公开(公告)号：US20020075630A1

公开(公告)日：2002-06-20

申请号：US09741302

申请日：2000-12-19

Applicant: Intel Corporation

Inventor： David G. Figueroa ,  Huong T. Do ,  Jorge Pedro Rodriguez ,  Michael Walk

IPC: H01G002/20

CPC classification number: H01G2/065 ,  H01L2924/15311

Abstract: A capacitor (FIGS. 6-9) includes one or more extended surface lands (604, 704, 804, 904, FIGS. 6-9). In one embodiment, each extended surface land is a land on a top or bottom surface of the capacitor, having a land length that is equal to at least 30% of the width (614, FIG. 6) of the capacitor or 20% of the length (914, FIG. 9) of the capacitor. When embedded within an integrated circuit package (1102, FIG. 11), two or more vias (1112) can be electrically connected to the extended surface lands (1108).

Abstract translation: 电容器（图6-9）包括一个或多个延伸的表面焊盘（604,704,804,904，图6-9）。 在一个实施例中，每个延伸的表面焊盘是电容器的顶部或底部表面上的焊盘，其具有等于电容器的宽度（614，图6）的至少30％的平台长度或20％ 电容器的长度（914，图9）。 当嵌入在集成电路封装（1102，图11）中时，两个或更多个通孔（1112）可以电连接到扩展表面焊盘（1108）。

公开(公告)号：US20020071256A1

公开(公告)日：2002-06-13

申请号：US09735956

申请日：2000-12-13

Applicant: Intel Corporation

Inventor： David G. Figueroa ,  Nicholas R. Watts

IPC: H05K001/18

CPC classification number: H01L23/5383 ,  H01L23/50 ,  H01L23/64 ,  H01L24/17 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K1/0231 ,  H05K1/185 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An electronic circuit package (400, FIG. 4) includes one or more trench vias (404, FIG. 4). Each trench via makes electrical contact with one or more terminals (526, FIG. 5) of a discrete device (520, FIG. 5) embedded within the package. A trench via can extend to a surface of the package, or one or more conventional vias (620, FIG. 6) formed within layers (602, FIG. 6) above or below the trench via can electrically connect the trench via, and thus the discrete device, to the surface of the package. The discrete device (520, FIG. 5) can be a capacitor, in one embodiment, providing decoupling capacitance to an integrated circuit load. Besides being implemented in a package, the trench vias also could be implemented in other types of electronic circuit housings (e.g., interposers, sockets, and printed circuit boards).

Abstract translation: 电子电路封装（图4中的400）包括一个或多个沟槽通孔（图4中的404）。 每个沟槽通孔与嵌入在封装内的分立器件（520，图5）的一个或多个端子（图5中的电极）进行电接触。 沟槽通孔可以延伸到封装的表面，或者形成在沟槽通孔上方或下方的层（602，图6）中的一个或多个传统通孔（620）可以电连接沟槽通孔，从而 分立器件，到封装的表面。 在一个实施例中，分立器件（图5中的520）可以是电容器，为集成电路负载提供去耦电容。 除了在封装中实现之外，沟槽通孔也可以实现在其他类型的电子电路外壳（例如，插入件，插座和印刷电路板）中。

公开(公告)号：US20030102523A1

公开(公告)日：2003-06-05

申请号：US10006188

申请日：2001-12-03

Applicant: Intel Corporation

Inventor： Yuan-Liang Li ,  David G. Figueroa ,  Chee-Yee Chung

IPC: H01L029/00

CPC classification number: H01G4/232

Abstract: A multilayer capacitor comprises separate terminals on at least three sides, and on as many as six sides. The capacitor can be fabricated in a large number of different configurations, types, and sizes, depending upon the target application. The separate terminals that are disposed on different sides of the capacitor can be readily coupled to a variety of different adjacent conductors, such as die terminals (including bumpless terminals or bars), IC package terminals (including pads or bars), and the terminals of adjacent discrete components. Methods of fabrication, as well as application of the capacitor to an electronic assembly, are also described.

Abstract translation: 多层电容器包括在至少三个侧面上以及多达六个侧面的分开的端子。 根据目标应用，电容器可以以大量不同的配置，类型和尺寸制造。 设置在电容器的不同侧上的单独的端子可以容易地耦合到各种不同的相邻导体，例如模具端子（包括无扰动端子或条），IC封装端子（包括焊盘或条），以及端子 相邻的分立元件。 还描述了制造方法以及将电容器应用于电子组件。

公开(公告)号：US20020151218A1

公开(公告)日：2002-10-17

申请号：US10176302

申请日：2002-06-20

Applicant: Intel Corporation

Inventor： David G. Figueroa ,  Chee-Yee Chung ,  Kristopher Frutschy ,  Farzaneh Yahyaei-Moayyed

IPC: H01R013/648 ,  H01R043/02

CPC classification number: H01R13/6585 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49211 ,  Y10T29/49222

Abstract: A socket (300, FIG. 3) includes a housing (302) with multiple openings (304) formed in the top surface. Each opening (304) provides access to conductive contacts (502, FIG. 5), which provide an electrical interface between a device that is inserted into the socket and the next level of interconnect (e.g., a PC board). Embedded within the socket is a conductive structure (310, FIG. 3). In one embodiment, the conductive structure is electrically connected to one or more ground conducting contacts (708, FIG. 7B). The conductive structure includes column walls (312), which run in parallel with columns of contacts, and row walls (314), which run in parallel with rows of contacts and which intersect the column walls. In this manner, the conductive structure forms multiple chambers (402, FIG. 4). Each signal carrying and power conducting contact is positioned within a chamber. Accordingly, the walls of the conductive structure function as a ground plane that surrounds the signal carrying and power conducting contacts.

Abstract translation: 插座（300，图3）包括具有形成在顶表面中的多个开口（304）的壳体（302）。 每个开口（304）提供对导电触点（502，图5）的访问，其提供插入到插座中的装置与下一级互连（例如，PC板）之间的电接口。 嵌入在插座内的是导电结构（图3中的310）。 在一个实施例中，导电结构电连接到一个或多个接地导电触头（图7B的708）。 导电结构包括与触点列平行延伸的柱壁（312）和平行于触点行并与柱壁相交的行壁（314）。 以这种方式，导电结构形成多个室（图4中的402）。 每个信号承载和电力传导触点位于一个室内。 因此，导电结构的壁用作围绕信号承载和电力传导触点的接地平面。

公开(公告)号：US20020089833A1

公开(公告)日：2002-07-11

申请号：US10076893

申请日：2002-02-14

Applicant: Intel Corporation

Inventor： P.R. Patel ,  Yuan-Liang Li ,  David G. Figueroa ,  Shamala Chickamenahalli ,  Huong T. Do

IPC: H05K007/02 ,  H05K007/06

CPC classification number: H05K1/141 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15192 ,  H05K1/0262 ,  H05K3/368 ,  H05K7/1092 ,  H05K2201/049 ,  H05K2201/10196 ,  H05K2201/10325 ,  H05K2201/10689 ,  H05K2201/10704 ,  H01L2224/0401

Abstract: An interposer includes two separate sets of pins, and inserts into two sockets on a printed circuit board. One set of pins supplies power to a step down converter (SDC) mounted on the interposer. The second set of pins provide inputs and outputs to an integrated circuit mounted on the interposer. One or more conductive traces in or on the interposer electrically connect an output of the SDC to an input of the integrated circuit, thus supplying regulated power to the integrated circuit through the interposer. The SDC and integrated circuit can be directly mounted on the interposer, or either or both can be mounted on packages that connect to the interposer. The SDC and integrated circuit can be flip chips or can be connected to the interposer or package using wirebonds. The packages can be pinned or connectable by solder bumps.

公开(公告)号：US20040039859A1

公开(公告)日：2004-02-26

申请号：US10224818

申请日：2002-08-21

Applicant: Intel Corporation

Inventor： Jiangqi He ,  Dong Zhong ,  David G. Figueroa ,  Yuan-Liang Li

IPC: G06F013/00

CPC classification number: H05K1/0245 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/09636 ,  H05K2201/09718

Abstract: A circuit board including a conductive plane, a first via and a second via. The first and second vias extend through the conductive plane such that there is no conductive material between the first and second vias within the conductive plane.

Abstract translation: 一种电路板，包括导电平面，第一通孔和第二通孔。 第一和第二通孔延伸通过导电平面，使得在导电平面内的第一和第二通孔之间不存在导电材料。

公开(公告)号：US20040021215A1

公开(公告)日：2004-02-05

申请号：US10209847

申请日：2002-07-31

Applicant: Intel Corporation

Inventor： Dong Zhong ,  Farzaneh Yahyaei-Moayyed ,  David G. Figueroa ,  Chris Baldwin ,  Jiangqi He ,  Yuan-Liang Li

IPC: H01L023/48 ,  H01L023/52

CPC classification number: H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An integrated circuit including a die, a power terminal and a ground terminal all mounted onto a substrate. The power terminal including a body and a first extension projecting from the body, and the ground terminal including a body and a second extension projecting from the body. The second extension on the ground terminal being adjacent to the first extension on the power terminal to offset inductance that is generated by supplying current to the die through the power terminal.

Abstract translation: 包括芯片，电源端子和接地端子的集成电路全部安装在基板上。 所述动力端子包括主体和从所述主体突出的第一延伸部，所述接地端子包括主体和从所述主体突出的第二延伸部。 接地端子上的第二延伸部分与电源端子上的第一延伸部相邻，以通过电源端子向管芯提供电流产生的偏移电感。

公开(公告)号：US20030230807A1

公开(公告)日：2003-12-18

申请号：US10167904

申请日：2002-06-12

Applicant: Intel Corporation

Inventor： Yuan-Liang Li ,  Jiangqi He ,  Dong Zhong ,  David G. Figueroa

IPC: H01L021/4763 ,  H01L023/48 ,  H01L029/40

CPC classification number: H01P3/081 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H05K1/0242 ,  H05K1/0245 ,  H05K1/0265 ,  H05K3/4644 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K2201/098 ,  H05K2203/0733 ,  H01L2924/00

Abstract: Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on nonconductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an nullI-shapednull or nullU-shapednull cross-section. In yet other embodiments, the trace configurations have nullT-shapednull and nullL-shapednull cross-sections.

Abstract translation: 用于承载高速数字差分信号的跟踪配置提供了降低的传导损耗和改善的信号完整性。 在一个实施例中，电路板具有布置在非导电材料上的第一组导电迹线和平行于第一组并设置在导电材料内的第二组导电迹线。 第二组与非导电材料与第一组分离。 第一组和第二组的相应迹线可以是堆叠配置。 在其他实施例中，导电材料可以设置在第一组和第二组的相应迹线之间，导致“I形”或“U形”横截面。 在其它实施例中，迹线构造具有“T形”和“L形”横截面。

公开(公告)号：US20040238942A1

公开(公告)日：2004-12-02

申请号：US10884644

申请日：2004-07-02

Applicant: Intel Corporation

Inventor： Kishore K. Chakravorty ,  Paul H. Wermer ,  David G. Figueroa ,  Debabrata Gupta

IPC: H01L023/48 ,  H01L029/40

CPC classification number: H01L23/49822 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15174 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/0306 ,  H05K1/141 ,  H05K1/162 ,  H05K1/185 ,  H05K3/4605 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/09309 ,  H05K2201/10674 ,  H01L2224/0401

Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.

公开(公告)号：US20030151146A1

公开(公告)日：2003-08-14

申请号：US10371659

申请日：2003-02-21

Applicant: Intel Corporation

Inventor： Chee-Yee Chung ,  David G. Figueroa ,  Robert L. Sankman

IPC: H01L023/48

CPC classification number: H05K1/141 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K1/0298 ,  H05K3/3436 ,  H05K3/366 ,  H05K2201/0919 ,  H05K2201/10446 ,  H05K2201/10454 ,  H05K2201/10674 ,  H05K2201/10719 ,  H01L2224/05599

Abstract: An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.