A semiconductor storage device includes a memory cell array 21 in which a plurality of memory elements are arranged and a program verify circuit 30. The memory element 1, 33 includes a gate electrode 104 formed on a semiconductor layer 102 via a gate insulator 103, a channel region arranged below the gate electrode 104, diffusion regions 107a, 107b that are located on opposite sides of the channel region and have a conductive type opposite to that of the channel region, and memory function bodies 109 that are located on opposite sides of the gate electrode 104 and have a function of retaining electric charge. A program load register 32 of the program verify circuit 30 eliminates a state that a memory element 33 which has initially been verified as having been correctly programmed needs to be further programmed.