An error rate of a bit synchronous circuit is decreased to a large extent by preventing following excessively the jitters included in input data. A phase detect circuit of a bit synchronous circuit includes a majority decision circuit. The majority decision circuit counts UP0 and DN0 signals as a phase comparison result of comparing phases by a UP0 counter and a DN0 counter for a period of time, and its count number is judged by a magnitude relation determination circuit. The magnitude relation determination circuit outputs an UP signal if the UP0 signal is majority, a DN signal if the DN0 signal is majority, and a FIX signal if the UP0 signal is equal to the DN0 signal. Accordingly, since it is possible to prevent following the jitters included in input data, etc., an error rate for bit synchronization can be reduced to a large extent.