发明申请
- 专利标题： Method for reducing defects in post passivation interconnect process
- 专利标题（中）： 减少后钝化互连过程中的缺陷的方法
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申请号： US10635621申请日： 2003-08-06
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公开(公告)号： US20050032353A1公开(公告)日： 2005-02-10
- 发明人: Hsi-Kuei Cheng , Hung-Ju Chien , Hsun-Chang Chan , Chu-Chang Chen , Ying-Lang Wang , Chin-Hao Su , Hsien-Ping Feng , Shih-Tzung Chang
- 申请人： Hsi-Kuei Cheng , Hung-Ju Chien , Hsun-Chang Chan , Chu-Chang Chen , Ying-Lang Wang , Chin-Hao Su , Hsien-Ping Feng , Shih-Tzung Chang
- 主分类号： H01L21/4763
- IPC分类号： H01L21/4763 ; H01L21/60 ; H01L23/31 ; H01L23/485
摘要：
A method of forming post passivation interconnects for an integrated circuit is disclosed. A passivation layer of a non-oxide material is formed over the integrated circuit. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer and a connection pattern is formed in the post passivation metal layer.
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