公开(公告)号：US07528478B2

公开(公告)日：2009-05-05

申请号：US11363813

申请日：2006-02-28

申请人： Hsi-Kuei Cheng ,  Hung-Ju Chien ,  Hsun-Chang Chan ,  Chu-Chang Chen ,  Ying-Lang Wang ,  Chin-Hao Su ,  Hsien-Ping Feng ,  Shih-Tzung Chang

发明人： Hsi-Kuei Cheng ,  Hung-Ju Chien ,  Hsun-Chang Chan ,  Chu-Chang Chen ,  Ying-Lang Wang ,  Chin-Hao Su ,  Hsien-Ping Feng ,  Shih-Tzung Chang

IPC分类号： H01L23/12

CPC分类号： H01L24/13 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00014

摘要： An integrated circuit having post passivation interconnections with a second connection pattern is disclosed. A passivation layer (preferably made of a non-oxide material) is formed over the integrated circuit already having a first plurality of contact pads in a first connection pattern. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer. A second plurality of contact pads as part of the second connection pattern is formed in the post passivation metal layer.

摘要翻译： 公开了具有第二连接图案的后钝化互连的集成电路。 在已经具有第一连接图案中的第一多个接触焊盘的集成电路上形成钝化层（优选由非氧化物材料制成）。 然后在钝化层上形成缓冲层。 缓冲层优选是氧化硅层，其厚度基本上小于钝化层的厚度。 后钝化金属层沉积在缓冲层上。 作为第二连接图案的一部分的第二多个接触焊盘形成在后钝化金属层中。

公开(公告)号：US20060145332A1

公开(公告)日：2006-07-06

申请号：US11363813

申请日：2006-02-28

申请人： Hsi-Kuei Cheng ,  Hung-Ju Chien ,  Hsun-Chang Chan ,  Chu-Chang Chen ,  Ying-Lang Wang ,  Chin-Hao Su ,  Hsien-Ping Feng ,  Shih-Tzung Chang

发明人： Hsi-Kuei Cheng ,  Hung-Ju Chien ,  Hsun-Chang Chan ,  Chu-Chang Chen ,  Ying-Lang Wang ,  Chin-Hao Su ,  Hsien-Ping Feng ,  Shih-Tzung Chang

IPC分类号： H01L23/12

CPC分类号： H01L24/13 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00014

摘要： An integrated circuit having post passivation interconnections with a second connection pattern is disclosed. A passivation layer (preferably made of a non-oxide material) is formed over the integrated circuit already having a first plurality of contact pads in a first connection pattern. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer. A second plurality of contact pads as part of the second connection pattern is formed in the post passivation metal layer.

摘要翻译： 公开了具有第二连接图案的后钝化互连的集成电路。 在已经具有第一连接图案中的第一多个接触焊盘的集成电路上形成钝化层（优选由非氧化物材料制成）。 然后在钝化层上形成缓冲层。 缓冲层优选是氧化硅层，其厚度基本上小于钝化层的厚度。 后钝化金属层沉积在缓冲层上。 作为第二连接图案的一部分的第二多个接触焊盘形成在后钝化金属层中。

公开(公告)号：US07777425B2

公开(公告)日：2010-08-17

申请号：US11809046

申请日：2007-05-30

申请人： Houng-Kuo Hsu ,  Chu-Chang Chen ,  Ching-Chuan Kuo

发明人： Houng-Kuo Hsu ,  Chu-Chang Chen ,  Ching-Chuan Kuo

IPC分类号： H05B41/16

CPC分类号： H05B41/245 ,  G06F2200/1612

摘要： A multi-lamp backlight system is disclosed. The multi-lamp backlight system includes a plurality of lamps, an inverter circuit and a current balance circuit. The inverter circuit is capable of converting a DC input signal to a pair of AC output signals, which have a 180 degree phase shift. The pair of AC output signals are delivered to the plurality of lamps. The current balance circuit is connected to the low voltage sides of the plurality of lamps for balancing the lamp currents.

摘要翻译： 公开了一种多灯背光系统。 多灯背光系统包括多个灯，逆变器电路和电流平衡电路。 逆变器电路能够将DC输入信号转换成具有180度相移的一对AC输出信号。 一对交流输出信号被传送到多个灯。 电流平衡电路连接到多个灯的低电压侧，用于平衡灯电流。

公开(公告)号：US06985222B2

公开(公告)日：2006-01-10

申请号：US10423379

申请日：2003-04-25

申请人： Hsi-Kuei Cheng ,  Chu-Chang Chen ,  Ting-Chun Wang ,  Szu-An Wu ,  Ying-Lang Wang ,  Hsien-Ping Feng

发明人： Hsi-Kuei Cheng ,  Chu-Chang Chen ,  Ting-Chun Wang ,  Szu-An Wu ,  Ying-Lang Wang ,  Hsien-Ping Feng

IPC分类号： G01N21/88

CPC分类号： G01N21/55 ,  G01N21/8422 ,  G01N2201/0227

摘要： A system and method for detecting chamber leakage by measuring the reflectivity of an oxidized thin film. In a preferred embodiment, a method of detecting leaks in a chamber includes providing a first monitor workpiece, placing the first monitor workpiece in the chamber, and forming at least one film on the first monitor workpiece. The reflectivity of the least one film of the first monitor workpiece is measured, wherein the reflectivity indicates whether there are leaks in the at least one seal of the chamber. In another embodiment, the method includes providing a second monitor workpiece, placing the second monitor workpiece in the chamber, and forming at least one film on the second monitor workpiece. The reflectivity of the at least one film of the second monitor workpiece is measured, and the second monitor workpiece film reflectivity is compared to the first monitor workpiece film reflectivity.

摘要翻译： 通过测量氧化薄膜的反射率来检测室泄漏的系统和方法。 在优选实施例中，检测腔室泄漏的方法包括提供第一监测工件，将第一监测器工件放置在腔室中，以及在第一监测器工件上形成至少一个膜。 测量第一监视器工件的至少一个膜的反射率，其中反射率指示在室的至少一个密封件中是否有泄漏。 在另一个实施例中，该方法包括提供第二监视器工件，将第二监视器工件放置在腔室中，以及在第二监视器工件上形成至少一个膜。 测量第二监测工件的至少一个膜的反射率，并将第二监测工件膜反射率与第一监测工件膜反射率进行比较。

公开(公告)号：US20080067951A1

公开(公告)日：2008-03-20

申请号：US11809046

申请日：2007-05-30

申请人： Houng-Kuo Hsu ,  Chu-Chang Chen ,  Ching-Chuan Kuo

发明人： Houng-Kuo Hsu ,  Chu-Chang Chen ,  Ching-Chuan Kuo

IPC分类号： H05B41/16 ,  G06F3/038 ,  G09G3/36

CPC分类号： H05B41/245 ,  G06F2200/1612

摘要： A multi-lamp backlight system is disclosed. The multi-lamp backlight system includes a plurality of lamps, an inverter circuit and a current balance circuit. The inverter circuit is capable of converting a DC input signal to a pair of AC output signals, which have a 180 degree phase shift. The pair of AC output signals are delivered to the plurality of lamps. The current balance circuit is connected to the low voltage sides of the plurality of lamps for balancing the lamp currents.

摘要翻译： 公开了一种多灯背光系统。 多灯背光系统包括多个灯，逆变器电路和电流平衡电路。 逆变器电路能够将DC输入信号转换成具有180度相移的一对AC输出信号。 一对交流输出信号被传送到多个灯。 电流平衡电路连接到多个灯的低电压侧，用于平衡灯电流。

公开(公告)号：US07026233B2

公开(公告)日：2006-04-11

申请号：US10635621

申请日：2003-08-06

申请人： Hsi-Kuei Cheng ,  Hung-Ju Chien ,  Hsun-Chang Chan ,  Chu-Chang Chen ,  Ying-Lang Wang ,  Chin-Hao Su ,  Hsien-Ping Feng ,  Shih-Tzung Chang

发明人： Hsi-Kuei Cheng ,  Hung-Ju Chien ,  Hsun-Chang Chan ,  Chu-Chang Chen ,  Ying-Lang Wang ,  Chin-Hao Su ,  Hsien-Ping Feng ,  Shih-Tzung Chang

IPC分类号： H01L21/50 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/461

CPC分类号： H01L24/13 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00014

摘要： A method of forming post passivation interconnects for an integrated circuit is disclosed. A passivation layer of a non-oxide material is formed over the integrated circuit. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer and a connection pattern is formed in the post passivation metal layer.

摘要翻译： 公开了一种形成用于集成电路的后钝化互连的方法。 在该集成电路上形成非氧化物材料的钝化层。 然后在钝化层上形成缓冲层。 缓冲层优选是氧化硅层，其厚度基本上小于钝化层的厚度。 在缓冲层上沉积钝化金属层，并且在后钝化金属层中形成连接图案。

公开(公告)号：US20050032353A1

公开(公告)日：2005-02-10

申请号：US10635621

申请日：2003-08-06

申请人： Hsi-Kuei Cheng ,  Hung-Ju Chien ,  Hsun-Chang Chan ,  Chu-Chang Chen ,  Ying-Lang Wang ,  Chin-Hao Su ,  Hsien-Ping Feng ,  Shih-Tzung Chang

发明人： Hsi-Kuei Cheng ,  Hung-Ju Chien ,  Hsun-Chang Chan ,  Chu-Chang Chen ,  Ying-Lang Wang ,  Chin-Hao Su ,  Hsien-Ping Feng ,  Shih-Tzung Chang

IPC分类号： H01L21/4763 ,  H01L21/60 ,  H01L23/31 ,  H01L23/485

CPC分类号： H01L24/13 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00014

摘要： A method of forming post passivation interconnects for an integrated circuit is disclosed. A passivation layer of a non-oxide material is formed over the integrated circuit. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer and a connection pattern is formed in the post passivation metal layer.

摘要翻译： 公开了一种形成用于集成电路的后钝化互连的方法。 在该集成电路上形成非氧化物材料的钝化层。 然后在钝化层上形成缓冲层。 缓冲层优选是氧化硅层，其厚度基本上小于钝化层的厚度。 在缓冲层上沉积钝化金属层，并且在后钝化金属层中形成连接图案。