Invention Application
- Patent Title: Semiconductor device and manufacturing method thereof
- Patent Title (中): 半导体装置及其制造方法
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Application No.: US10929727Application Date: 2004-08-31
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Publication No.: US20050073004A1Publication Date: 2005-04-07
- Inventor: Masahito Onda , Hirotoshi Kubo , Shouji Miyahara , Hiroyasu Ishida
- Applicant: Masahito Onda , Hirotoshi Kubo , Shouji Miyahara , Hiroyasu Ishida
- Applicant Address: JP Moriguchi-city
- Assignee: Sanyo Electric Co., Ltd.
- Current Assignee: Sanyo Electric Co., Ltd.
- Current Assignee Address: JP Moriguchi-city
- Priority: JP2003-333889 20030925
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/336 ; H01L21/8234 ; H01L29/40 ; H01L29/739 ; H01L29/76 ; H01L29/78 ; H01L29/861

Abstract:
Conventional power MOSFETs enables prevention of an inversion in a surrounding region surrounding the outer periphery of an element region by a wide annular layer and a wide sealed metal. Since, resultantly, the area of the surrounding region is large, increase in the element region has been restrained. A semiconductor device is hereby provided which has an inversion prevention region containing an MIS (MOS) structure. The width of polysilicon for the inversion prevention region is large enough to prevent an inversion since the area of an oxide film can be increased by the depth of the trench. By this, leakage current can be reduced even though the area of the region surrounding the outer periphery of the element region is not enlarged. In addition, since the element region is enlarged, on-state resistance of the MOSFET can be reduced.
Public/Granted literature
- US07230300B2 Semiconductor device with peripheral trench Public/Granted day:2007-06-12
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