发明申请
US20050077936A1 Circuit and method for reducing jitter in a PLL of high speed serial links
失效
用于降低高速串行链路PLL的抖动的电路和方法
- 专利标题： Circuit and method for reducing jitter in a PLL of high speed serial links
- 专利标题（中）： 用于降低高速串行链路PLL的抖动的电路和方法
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申请号： US10685022申请日： 2003-10-14
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公开(公告)号： US20050077936A1公开(公告)日： 2005-04-14
- 发明人: Hayden Cranford , Stacy Garvin , Vernon Norman , Todd Rasmus
- 申请人： Hayden Cranford , Stacy Garvin , Vernon Norman , Todd Rasmus
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 主分类号： H03L7/10
- IPC分类号： H03L7/10 ; H03L7/00
摘要：
Aspects for reducing jitter in a PLL of a high speed serial link are described. The aspects include examining at least one parameter related to performance of a voltage controlled oscillator (VCO) in the PLL, and controlling adjustment of a supply voltage to the VCO based on the examining. A regulator control circuit performs the examining and controlling.
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