公开(公告)号：US20070242741A1

公开(公告)日：2007-10-18

申请号：US11405997

申请日：2006-04-18

申请人： Juan Carballo ,  Hayden Cranford ,  Gareth Nicholls ,  Vernon Norman ,  Martin Schmatz

发明人： Juan Carballo ,  Hayden Cranford ,  Gareth Nicholls ,  Vernon Norman ,  Martin Schmatz

IPC分类号： H03H7/30

CPC分类号： H04L25/03063

摘要： Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a decision feedback equalizer along with the appropriate (CDR) loop phase detector to maintain a single sample per bit requirement. The incoming voltage is converted to a current and connected to a current summing node. Weighted currents determined by the values of previously detected bits and their respective feedback coefficients are also connected to this node. Additionally, the summed currents is integrated and converted to a voltage. A sampler is utilized to make a bit decision based on the resulting voltage. After sampling, the integrator is reset before analysis of the next bit. The necessary amplification is achieved by maximizing the sensitivity of the latch, using integration in front of the data latch.

摘要翻译： 公开了一种在接收机中利用/产生一个每位采样的判决反馈均衡器（DFE）时钟和数据恢复（CDR）架构的接收器电路，方法和设计架构，并且降低了误码率（BER ）。 集成接收机与决策反馈均衡器以及适当的（CDR）环路相位检测器相结合，以保持每位需求的单个采样。 输入电压被转换为电流并连接到电流求和节点。 由先前检测到的位及其各自的反馈系数的值确定的加权电流也连接到该节点。 另外，总和电流被积分并转换成电压。 采样器用于基于所得到的电压进行位决定。 采样后，积分器在分析下一位之前被复位。 通过使用在数据锁存器前面的积分来最大化锁存器的灵敏度来实现必要的放大。

公开(公告)号：US20070069793A1

公开(公告)日：2007-03-29

申请号：US11235758

申请日：2005-09-27

申请人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman ,  Samuel Ray ,  Wayne Utter

发明人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman ,  Samuel Ray ,  Wayne Utter

IPC分类号： G06F1/04

CPC分类号： G06F1/04

摘要： A differential clock signal gating method and system is provided, wherein a clock buffer circuit control path develops a clock gating signal with a timing relationship to a clock signal. The clock gating signal gates a buffer on the clock buffer circuit controlled path in communication with the clock signal responsive to a first clock signal pulse negative half. The buffer provides second and successive clock signal pulses occurring immediately and sequentially after the first clock signal pulse as a buffer clock signal output to a second buffer stage in a second stage clock path, each having the nominal clock amplitude and the nominal clock pulse width of the clock signal without jitter.

摘要翻译： 提供了一种差分时钟信号门控方法和系统，其中时钟缓冲器电路控制路径产生与时钟信号的定时关系的时钟门控信号。 时钟门控信号将响应于第一时钟信号脉冲负半部分的与时钟信号通信的时钟缓冲器电路控制路径上的缓冲器门控。 缓冲器提供在第一时钟信号脉冲之后立即和顺序发生的第二和连续时钟信号脉冲，作为输出到第二级时钟路径中的第二缓冲级的缓冲时钟信号，每个具有标称时钟幅度和标称时钟脉冲宽度 时钟信号无抖动。

公开(公告)号：US20070047589A1

公开(公告)日：2007-03-01

申请号：US11211125

申请日：2005-08-24

申请人： Bobak Modaress-Razavi ,  Vernon Norman

发明人： Bobak Modaress-Razavi ,  Vernon Norman

IPC分类号： H04J3/06 ,  H04J3/04

CPC分类号： H03M9/00 ,  H04J3/0685

摘要： A serializer/deserializer (SERDES) receiver circuit designed to support multiple serial data rates (full, half, and quarter rates) based on user selection, while requiring substantially minimal amounts of additional logic and complexity within the core logic functions and analog circuits of a full rate SERDES. Over-sampled data from the analog block is provided to support each of the different rates, and the data is stored in three preliminary rate registers, one for full rate, one for half rate and one for quarter rate. In full rate mode, all samples coming from the analog circuits are utilized. In half rate and quarter rate modes, one out of every two samples and one out of every four samples is utilized, respectively. The selected samples are converted to parallel data by core logic functions, which are provided a single clock signal corresponding to the particular mode of operation.

摘要翻译： 串行器/解串器（SERDES）接收器电路，其设计用于基于用户选择来支持多个串行数据速率（全，半和四分之一速率），同时在核心逻辑功能和模拟电路中需要基本上最小量的附加逻辑和复杂性 全速SERDES。 提供来自模拟块的过采样数据以支持每个不同的速率，并且数据存储在三个初始速率寄存器中，一个用于全速率，一个一半速率，一个用于四分之一速率。 在全速率模式下，利用来自模拟电路的所有采样。 在半速率和四分之一速率模式下，分别利用了每两个样本中的一个和四个样本中的一个。 所选样本通过核心逻辑功能转换为并行数据，其被提供与特定操作模式对应的单个时钟信号。

公开(公告)号：US20060029177A1

公开(公告)日：2006-02-09

申请号：US11249851

申请日：2005-10-13

申请人： Hayden Cranford ,  Vernon Norman ,  Martin Schmatz

发明人： Hayden Cranford ,  Vernon Norman ,  Martin Schmatz

IPC分类号： H03D3/24

CPC分类号： H03L7/08 ,  H03L7/095 ,  H03L7/0995 ,  H03L7/10 ,  H04L7/0337 ,  H04L2027/0067

摘要： A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL), a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.

公开(公告)号：US20080112521A1

公开(公告)日：2008-05-15

申请号：US11966438

申请日：2007-12-28

申请人： Martin Schmatz ,  Hayden Cranford ,  Vernon Norman

发明人： Martin Schmatz ,  Hayden Cranford ,  Vernon Norman

IPC分类号： H04L7/00

CPC分类号： H03L7/091 ,  H03L7/0814 ,  H03L7/089 ,  H04L7/0331

摘要： The invention is directed to a clock data recovery system for resampling a clock signal according to an incoming data signal. The clock data recovery system comprises a clock generator for generating the clock signal and a phase adjustment unit for generating sampling phases dependent on a phase adjustment control signal. It also comprises a data sampling unit operable to generate a stream of input samples and an edge detector for generating therefrom an internal early signal and an internal late signal. A phase adjustment control unit is disposed for generating under use of the early signal and the late signal the phase adjustment control signal. The phase adjustment control unit is feedable with an external early/late signal and/or comprises an output for delivering an export early/late signal.

摘要翻译： 本发明涉及一种用于根据输入数据信号重新采样时钟信号的时钟数据恢复系统。 时钟数据恢复系统包括用于产生时钟信号的时钟发生器和用于根据相位调整控制信号产生采样相位的相位调整单元。 它还包括可操作以产生输入样本流的数据采样单元和用于从其产生内部早期信号和内部迟滞信号的边缘检测器。 设置相位调整控制单元，用于在早期信号的使用下产生相位调整控制信号，并且延迟信号。 相位调整控制单元可以用外部早/晚信号进给，和/或包括用于传送出口早/晚信号的输出。

公开(公告)号：US20060209944A1

公开(公告)日：2006-09-21

申请号：US11079952

申请日：2005-03-15

申请人： Juan Carballo ,  Hayden Cranford ,  Gareth Nicholls ,  Vernon Norman ,  Brian Schuh

发明人： Juan Carballo ,  Hayden Cranford ,  Gareth Nicholls ,  Vernon Norman ,  Brian Schuh

IPC分类号： H04B17/00 ,  H03D1/04

CPC分类号： H04B17/382 ,  H04B17/24 ,  H04B17/345

摘要： A method, circuit and system for altering the power consumption in communication links. A type of noise and an amount of jitter in a signal transmitted across a communication link is measured. Upon determining the contribution of the measured noise to the measured jitter in the signal, the measured noise is classified based on such contribution and the intensity of the measured jitter. The power consumption in a component(s) of the communication link may be adjusted based on the classification of the measured noise. For example, if the measured noise is classified as being a low amount of noise, then the power consumption of the component(s) may be reduced such as by lowering the voltage of the power supply and/or reducing the complexity of the circuitry. By reducing the power consumption when the communication link is not subject to the worst-case condition, a savings in power consumption may be made.

公开(公告)号：US20050195863A1

公开(公告)日：2005-09-08

申请号：US10791175

申请日：2004-03-02

申请人： Hayden Cranford ,  Gareth Nicholls ,  Bobak Modaress-Razavi ,  Vernon Norman ,  Martin Schmatz

发明人： Hayden Cranford ,  Gareth Nicholls ,  Bobak Modaress-Razavi ,  Vernon Norman ,  Martin Schmatz

IPC分类号： H03L7/07 ,  H03L7/081 ,  H03L7/093 ,  H04L27/00 ,  H04J3/06

CPC分类号： H03L7/0814 ,  H03L7/07 ,  H04L2027/0065 ,  H04L2027/0067

摘要： Aspects of providing automatic adaptation to frequency offsets in high speed serial links are described. First signals for phase adjusts in a receiver link are adjusted by detecting trends in the first signals to generate second signals, the second signals improving a rate of compensation for the frequency offsets by the phase adjusts. An up/down counter is included for counting signals for phase adjustments by a clock-data-recovery loop of a serial receiver. An adder is coupled to the up/down counter and outputs accumulated data indicative of a trend in the phase adjustments. Combinatorial logic coupled to the adder adapts the signals based on the accumulated data.

摘要翻译： 描述了在高速串行链路中提供对频偏的自动适配的方面。 通过检测第一信号中的趋势来产生第二信号来调整在接收机链路中进行相位调整的第一信号，第二信号通过相位调整来提高对频偏的补偿率。 包括一个向上/向下计数器，用于通过串行接收器的时钟数据恢复环来对信号进行相位调整。 加法器耦合到上/下计数器并输出指示相位调整趋势的累加数据。 耦合到加法器的组合逻辑基于累积数据来适配信号。

公开(公告)号：US20050111536A1

公开(公告)日：2005-05-26

申请号：US10720974

申请日：2003-11-24

申请人： Hayden Cranford ,  Marcel Kossel ,  Vernon Norman ,  Martin Schmatz

发明人： Hayden Cranford ,  Marcel Kossel ,  Vernon Norman ,  Martin Schmatz

IPC分类号： H04B3/46 ,  H04L1/20 ,  H04L25/06

CPC分类号： H04L25/068 ,  H04B3/462 ,  H04L1/205

摘要： The method for determining jitter of a signal in a serial link according to the invention comprising the following steps: First, a section of the signal transmitted via a transmission channel is sampled at different sampling times. The total number of edges in the section is determined. The neighboring sample values are analyzed and from that a statistical value is formed. From the statistical value and the total number of edges a figure of merit is determined. Finally, by means of a look-up table or a jitter-versus-figure of merit curve, the total jitter corresponding to the figure of merit is derived.

摘要翻译： 根据本发明的用于确定串行链路中的信号的抖动的方法包括以下步骤：首先，经由传输信道发送的信号的一部分在不同的采样时间被采样。 确定该部分中的边缘总数。 分析相邻的样本值，并从中形成统计值。 从统计值和总边缘数确定品质因数。 最后，通过查询表或优点曲线的抖动对数值，推导出与品质因数对应的总抖动。

公开(公告)号：US20070096720A1

公开(公告)日：2007-05-03

申请号：US11262101

申请日：2005-10-28

申请人： Steven Clements ,  William Cornwell ,  Carrie Cox ,  Hayden Cranford ,  Vernon Norman

发明人： Steven Clements ,  William Cornwell ,  Carrie Cox ,  Hayden Cranford ,  Vernon Norman

IPC分类号： G01R31/28

CPC分类号： G01R35/007 ,  Y10T29/49004 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49174

摘要： Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.

摘要翻译： 将被测器件（DUT）的输出阻抗基本上精确地校准到允许阻抗的预定范围内。 DUT是源极串行端接（SST）串行链路发射机的一部分，其中当并联支路的特定晶体管导通时，并联晶体管的两个分支都提供阻抗值。 将阻抗值加到串联电阻器上以提供输出阻抗。 DUT由与电阻器串联的并行晶体管的一个分支组成。 将DUT的输出阻抗与参考电阻的电阻进行比较，并且比较器根据输出阻抗是否落在参考电阻的预设百分比方差内提供控制信号。 控制信号由FSM（有限状态机）进行处理，FSM单独打开或关闭并联支路内的晶体管，直到DUT阻抗值落在所需范围内。

公开(公告)号：US20060045224A1

公开(公告)日：2006-03-02

申请号：US10915790

申请日：2004-08-11

申请人： Hayden Cranford ,  Gareth Nicholls ,  Vernon Norman ,  Martin Schmatz ,  Karl Selander ,  Michael Sorna

发明人： Hayden Cranford ,  Gareth Nicholls ,  Vernon Norman ,  Martin Schmatz ,  Karl Selander ,  Michael Sorna

IPC分类号： H04L7/00

CPC分类号： H04L7/0337 ,  H03L7/091 ,  H03L2207/50

摘要： Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by slowing the clock rate with respect to the sampling clock. For instance, the slower clock rate may be implemented by dividing the frequency of the sampling clock by a number such as 128, slowing a sampling clock frequency designed to handle multiple gigabits per second (Gbps) to a frequency of less than one kilohertz (Khz). In addition to the reduced power consumption realized by operating at a lower frequency, the slower clock rate allows components of the CDR loop circuitry to operate a lower operating voltage reducing power consumption by the CDR loop even more.

摘要翻译： 公开了基于从输入数据信号导出的数据样本子集或值的确定时钟和数据恢复（CDR）循环的采样时钟的相位调整的方法和装置。 具体地，实施例通过相对于采样时钟减慢时钟速率来扩展CDR环路。 例如，较慢的时钟速率可以通过将采样时钟的频率除以诸如128的数字来实现，将被设计为处理多吉比特每秒（Gbps）的采样时钟频率减慢到小于1千赫兹的频率（Khz ）。 除了通过以较低频率操作实现的降低的功耗之外，较慢的时钟速率允许CDR环路电路的组件操作较低的工作电压，从而降低CDR环路的功耗。