发明申请
- 专利标题： Method of fabricating vertical integrated circuits
- 专利标题（中）： 制造垂直集成电路的方法
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申请号： US11020753申请日： 2004-12-23
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公开(公告)号： US20050112848A1公开(公告)日： 2005-05-26
- 发明人: Sadeg Faris
- 申请人： Sadeg Faris
- 申请人地址： US NY Elmsford 10523
- 专利权人： Reveo, Inc.
- 当前专利权人： Reveo, Inc.
- 当前专利权人地址： US NY Elmsford 10523
- 主分类号： B81C1/00
- IPC分类号： B81C1/00 ; G01R31/01 ; H01L21/66 ; H01L21/00 ; H01L21/30 ; H01L21/46 ; H01L21/76
摘要：
A method for fabricating a vertical integrated circuit is disclosed. Integrated circuits are fabricated on a substrate with layers of predetermined weak and strong bond regions where deconstructed layers of integrated circuits are fabricated at or on the weak bond regions. The layers are then peeled and subsequently bonded to produce a vertical integrated circuit. An arbitrary number of layers can be bonded and stacked in to a separate vertical integrated circuit. Also disclosed are methods of creating edge interconnects and vias through the substrate to form interconnections between layers and devices thereon.
公开/授权文献
- US07145219B2 Vertical integrated circuits 公开/授权日：2006-12-05
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