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    Electrochemical lithography memory system and method
    1.
    发明授权
    Electrochemical lithography memory system and method 失效
    电化学光刻记忆系统及方法

    公开(公告)号：US07388767B2

    公开(公告)日：2008-06-17

    申请号：US11180897

    申请日：2005-07-13

    申请人： Sadeg M. Faris

    发明人： Sadeg M. Faris

    IPC分类号： G11C19/08

    CPC分类号： G11B9/08 ,  G11C13/0009 ,  G11C2213/71

    摘要： Electronic memory devices fabricated using nanolithography techniques enables rapid and reliable storage of data on a substrate. One such device includes a memory access head, which includes a conductive member and an insulative member. The conductive member includes a proximal conductive tip, a distal conductive tip, and a body portion. The body portion is embedded in the insulative member. The device further includes a substrate adjacent to the distal conductive tip, an electrolyte disposed between the distal conductive tip and the substrate; and a microchip in communication with the proximal conductive tip.

    摘要翻译： 使用纳米光刻技术制造的电子存储器件使得能够在衬底上快速可靠地存储数据。 一种这样的装置包括存储器存取头，其包括导电构件和绝缘构件。 导电构件包括近端导电尖端，远端导电尖端和主体部分。 主体部分嵌入在绝缘构件中。 所述装置还包括邻近所述远侧导电尖端的基底，设置在所述远侧导电尖端和所述基底之间的电解质; 以及与近端导电尖端连通的微芯片。

    Layered electrochemical cell and manufacturing method therefor
    2.
    发明授权
    Layered electrochemical cell and manufacturing method therefor 失效
    分层电化学电池及其制造方法

    公开(公告)号：US07377948B2

    公开(公告)日：2008-05-27

    申请号：US10455228

    申请日：2003-06-05

    申请人： Sadeg M. Faris

    发明人： Sadeg M. Faris

    IPC分类号： H01M2/00 ,  H01M2/14

    CPC分类号： H01M8/241 ,  H01M8/00 ,  H01M8/24 ,  H01M8/2404 ,  H01M8/2465 ,  H01M10/0436 ,  Y02P70/56 ,  Y10T29/49108 ,  Y10T29/49112

    摘要： Methods of the present invention are provided for forming a plurality of electrochemical cell layers, each cell layer generally including a pair of electrodes and a separator electrically insulating the pair of electrodes. Cells of a desired size are formed by slicing the laminar sheet through both opposing major surfaces. In certain embodiments, individual cells are defined by fill regions, filled with removable substances. Thus, when the cells are sliced, individual cells and in certain embodiments current collectors or conductors are exposed with minimal or no further processing. In other embodiments, fluid access channels or porous layers are filled with removable substances. Thus, when the cells are sliced, structural support is provided for the intended void regions.

    摘要翻译： 提供本发明的方法用于形成多个电化学电池层，每个电池层通常包括一对电极和使该对电极电绝缘的隔板。 所需尺寸的细胞是通过将层状片通过两个相对的主表面进行切片而形成的。 在某些实施方案中，单个细胞由填充有可除去物质的填充区限定。 因此，当细胞被切片时，单个细胞并且在某些实施方案中，电流收集器或导体暴露于最小或不进一步的处理。 在其它实施例中，流体通道或多孔层填充有可除去的物质。 因此，当细胞切片时，为预期的空隙区域提供结构支撑。

    Backlight units for liquid crystal displays
    3.
    发明授权
    Backlight units for liquid crystal displays 失效

    公开(公告)号：US07148513B2

    公开(公告)日：2006-12-12

    申请号：US09885742

    申请日：2001-06-20

    申请人： Zhan He ,  Sadeg M. Faris

    发明人： Zhan He ,  Sadeg M. Faris

    IPC分类号： H01L27/15

    CPC分类号： G02F1/13362 ,  G02F1/133615

    摘要： A novel backlight is provided for a liquid crystal display (LCD). The backlight of this invention includes an organic electroluminescent (EOL) device and a cholesteric liquid crystal (CLC) polarizing device. This invention is also an LCD. The backlight of the present invention provides for highly efficiency and bright LCDs. This invention further provides for the production of ultra-thin and lightweight LCDs.

    Electron beam excited superconducting analog-to-digital converter
    6.
    发明授权
    Electron beam excited superconducting analog-to-digital converter 失效
    电子束激发超导模数转换器

    公开(公告)号：US06980142B2

    公开(公告)日：2005-12-27

    申请号：US10657736

    申请日：2003-09-08

    申请人： Sadeg M. Faris

    发明人： Sadeg M. Faris

    IPC分类号： H03M1/00 ,  H03M1/32

    CPC分类号： H03M1/32

    摘要： A system and method for converting an analog voltage signal to a digital representation at high speeds, known as an analog to digital converter (A/D converter), is provided in the form of an N-bit A/D converter, made by N superconducting, preferably HTC, transmission lines. The N lines are arranged adjacently and in parallel with each other. On each line 2N−1 Josephson Junctions (JJs) are embedded in series. The JJs form a matrix over the configuration of the N superconducting transmission lines. A scanning electron beam is made to impinge on this arrangement across the lines at a high frequency, while it is deflected by the applied voltage signal along the direction of the lines. A voltage step is generated upon hitting any one of the JJs. In this manner upon each cross-scanning of the beam, an N-bit step voltage pattern is generated on the lines.

    摘要翻译： 以模拟数字转换器（A / D转换器）的形式将模拟电压信号转换为高速数字显示的系统和方法以N位A / D转换器的形式提供，由N 超导，优选HTC，传输线。 N行相互并排设置。 在每条线上，串联嵌入了N-1个约瑟夫逊接头（JJ）。 JJ在N超导传输线的配置上形成矩阵。 使扫描电子束以高频撞击在该布置上，同时沿着线的方向被施加的电压信号偏转。 在击中任何一个JJ时产生电压阶跃。 以这种方式在每次交叉扫描光束时，在线上产生N位步进电压模式。

    Method of fabricating vertical integrated circuits
    9.
    发明申请
    Method of fabricating vertical integrated circuits 失效
    制造垂直集成电路的方法

    公开(公告)号：US20050112848A1

    公开(公告)日：2005-05-26

    申请号：US11020753

    申请日：2004-12-23

    申请人： Sadeg Faris

    发明人： Sadeg Faris

    IPC分类号： B81C1/00 ,  G01R31/01 ,  H01L21/66 ,  H01L21/00 ,  H01L21/30 ,  H01L21/46 ,  H01L21/76

    CPC分类号： B81C1/00238 ,  B81C1/0038 ,  B81C2201/019 ,  G01R31/01 ,  H01L22/20 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/014 ,  Y10S438/977 ,  H01L2924/00

    摘要： A method for fabricating a vertical integrated circuit is disclosed. Integrated circuits are fabricated on a substrate with layers of predetermined weak and strong bond regions where deconstructed layers of integrated circuits are fabricated at or on the weak bond regions. The layers are then peeled and subsequently bonded to produce a vertical integrated circuit. An arbitrary number of layers can be bonded and stacked in to a separate vertical integrated circuit. Also disclosed are methods of creating edge interconnects and vias through the substrate to form interconnections between layers and devices thereon.

    摘要翻译： 公开了一种用于制造垂直集成电路的方法。 集成电路制造在具有预定的弱结合区域和强结合区域的衬底上，其中集成电路的解构层在弱键区域处或其上制造。 然后将这些层剥离并随后结合以产生垂直集成电路。 任意数量的层可以结合并堆叠到单独的垂直集成电路中。 还公开了通过衬底产生边缘互连和通孔以在其上的层和器件之间形成互连的方法。