发明申请
- 专利标题： Method and apparatus of lowering I/O bus power consumption
- 专利标题（中）： 降低I / O总线功耗的方法和装置
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申请号： US10810119申请日： 2004-03-25
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公开(公告)号： US20050144488A1公开(公告)日： 2005-06-30
- 发明人: Victor Lee , Phanindra Mannava , Akhilesh Kumar , Sanjay Dabral
- 申请人： Victor Lee , Phanindra Mannava , Akhilesh Kumar , Sanjay Dabral
- 主分类号： G06F1/32
- IPC分类号： G06F1/32 ; G06F1/26
摘要：
The current method and apparatus provides a novel approach to manage the power consumption of a high speed I/O interface by selectively turning off non-essential portions of the interface. Here only part of the interface is powered off as compared to the whole interface being turned off. From the upper layers (protocol/system) perspective, the interface is always “on”. Thus, this mechanism reduces link power by selectively turning off portions of the link, yet allowing for fast wake up in an interface power management architecture.