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54 条记录 (耗时 0.021 秒)

    Retraining derived clock receivers
    1.
    发明申请
    Retraining derived clock receivers 有权
    再培训派生的时钟接收器

    公开(公告)号：US20050022100A1

    公开(公告)日：2005-01-27

    申请号：US10623605

    申请日：2003-07-22

    申请人： Victor Lee ,  Phanindra Mannava ,  Akhilesh Kumar ,  Sanjay Dabral

    发明人： Victor Lee ,  Phanindra Mannava ,  Akhilesh Kumar ,  Sanjay Dabral

    IPC分类号： H04L1/00 ,  H04L25/49 ,  H04Q11/04 ,  G08C25/00 ,  G06F11/00 ,  G06F11/30 ,  H03M13/00

    CPC分类号： H04L1/0061 ,  H04J2203/0089 ,  H04L1/0072 ,  H04L25/4906 ,  H04L2001/0094

    摘要： Systems and methods of retraining a receiver provide for determining a minimum transition density for a derived clock data link to the receiver. A retraining flit is generated based on the minimum transition density. In one approach, the retraining flit is generated by defining control data and payload data for the retraining flit. Error detection data is determined for the retraining flit based on the control and the payload data. The control data, the payload data and the error detection data have sufficient transitions to meet the minimum transition density.

    摘要翻译： 重新接收接收机的系统和方法提供用于确定到接收机的导出时钟数据链路的最小转换密度。 基于最小过渡密度产生再培训。 在一种方法中，通过为再训练飞行定义控制数据和有效载荷数据来产生再训练飞行。 基于控制和有效载荷数据确定重新训练飞行的错误检测数据。 控制数据，有效载荷数据和误差检测数据具有足够的过渡以满足最小转换密度。

    Method and apparatus of lowering I/O bus power consumption
    2.
    发明申请
    Method and apparatus of lowering I/O bus power consumption 审中-公开
    降低I / O总线功耗的方法和装置

    公开(公告)号：US20050144488A1

    公开(公告)日：2005-06-30

    申请号：US10810119

    申请日：2004-03-25

    申请人： Victor Lee ,  Phanindra Mannava ,  Akhilesh Kumar ,  Sanjay Dabral

    发明人： Victor Lee ,  Phanindra Mannava ,  Akhilesh Kumar ,  Sanjay Dabral

    IPC分类号： G06F1/32 ,  G06F1/26

    CPC分类号： G06F1/3209 ,  G06F1/3253 ,  Y02D10/151 ,  Y02D50/20

    摘要： The current method and apparatus provides a novel approach to manage the power consumption of a high speed I/O interface by selectively turning off non-essential portions of the interface. Here only part of the interface is powered off as compared to the whole interface being turned off. From the upper layers (protocol/system) perspective, the interface is always “on”. Thus, this mechanism reduces link power by selectively turning off portions of the link, yet allowing for fast wake up in an interface power management architecture.

    摘要翻译： 目前的方法和装置提供了一种新颖的方法，通过选择性地关闭界面的非必要部分来管理高速I / O接口的功耗。 与整个接口关闭相比，这里只有部分接口掉电。 从上层（协议/系统）的角度来看，界面总是“开”。 因此，该机制通过选择性地关闭链路的部分而减少链路功率，但允许在接口电源管理架构中快速唤醒。

    Method, system, and apparatus for system level initialization
    5.
    发明申请
    Method, system, and apparatus for system level initialization 有权
    用于系统级初始化的方法，系统和装置

    公开(公告)号：US20060126656A1

    公开(公告)日：2006-06-15

    申请号：US11011801

    申请日：2004-12-13

    申请人： Mani Ayyar ,  Srinivas Chennupaty ,  Akhilesh Kumar ,  Doddaballapur Jayasimha ,  Murugasamy Nachimuthu ,  Phanindra Mannava

    发明人： Mani Ayyar ,  Srinivas Chennupaty ,  Akhilesh Kumar ,  Doddaballapur Jayasimha ,  Murugasamy Nachimuthu ,  Phanindra Mannava

    IPC分类号： H04L12/42

    CPC分类号： H04L67/125 ,  H04L69/324

    摘要： Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.

    摘要翻译： 讨论了用于系统和组件在点对点架构中的多个初始化技术。 因此，这些技术允许根据平台（如桌面，移动，小型服务器，大型服务器等）的需求以及诸如IA32 / IPF处理器之类的组件类型来定制灵活的系统/套接字层参数 ，存储器控制器，IO集线器等。此外，该技术有助于以正确的一组POC值加电，因此避免了多次热复位并提高了启动时间。 在一个实施例中，可以消除保存新值的寄存器，例如在复位期间驱动的配置值（CVDR）和在复位期间捕获的配置值（CVCR）。 例如，POC值可以来自以下内容：平台输入时钟到核心时钟比率，启用/禁用LT，可配置重新启动，刻录初始化模式，禁用超线程，系统BSP插槽指示和平台拓扑索引。

    Retraining derived clock receivers
    6.
    发明授权
    Retraining derived clock receivers 有权
    再培训派生的时钟接收器

    公开(公告)号：US07320094B2

    公开(公告)日：2008-01-15

    申请号：US10623605

    申请日：2003-07-22

    申请人： Victor W. Lee ,  Phanindra K. Mannava ,  Akhilesh Kumar ,  Sanjay Dabral

    发明人： Victor W. Lee ,  Phanindra K. Mannava ,  Akhilesh Kumar ,  Sanjay Dabral

    IPC分类号： H04L7/00

    CPC分类号： H04L1/0061 ,  H04J2203/0089 ,  H04L1/0072 ,  H04L25/4906 ,  H04L2001/0094

    摘要： Systems and methods of retraining a receiver provide for determining a minimum transition density for a derived clock data link to the receiver. A retraining flit is generated based on the minimum transition density. In one approach, the retraining flit is generated by defining control data and payload data for the retraining flit. Error detection data is determined for the retraining flit based on the control and the payload data. The control data, the payload data and the error detection data have sufficient transitions to meet the minimum transition density.

    摘要翻译： 重新接收接收机的系统和方法提供用于确定到接收机的导出时钟数据链路的最小转换密度。 基于最小过渡密度产生再培训。 在一种方法中，通过为再训练飞行定义控制数据和有效载荷数据来产生再训练飞行。 基于控制和有效载荷数据确定重新训练飞行的错误检测数据。 控制数据，有效载荷数据和误差检测数据具有足够的过渡以满足最小转换密度。

    MODULAR DECOUPLED CROSSBAR FOR ON-CHIP ROUTER
    9.
    发明申请
    MODULAR DECOUPLED CROSSBAR FOR ON-CHIP ROUTER 有权
    用于片上路由器的模块化解交叉

    公开(公告)号：US20140376557A1

    公开(公告)日：2014-12-25

    申请号：US13994801

    申请日：2012-02-09

    申请人： Dongkonk Park ,  Aniruddha Vaidya ,  Akhilesh Kumar ,  Mani Azimi

    发明人： Dongkonk Park ,  Aniruddha Vaidya ,  Akhilesh Kumar ,  Mani Azimi

    IPC分类号： H04L12/933

    CPC分类号： H04L49/101 ,  G06F15/17381 ,  G06F15/7825 ,  H04L49/109 ,  H04L49/15 ,  Y02D10/12 ,  Y02D10/13

    摘要： Layout-aware modular decoupled crossbar and router for on-chip interconnects and associated micro-architectures and methods of operation. A crossbar and router architecture called MoDe-X (Modular Decoupled Crossbar) is disclosed that supports 5-port routing for use in 2D mesh interconnects and is implemented through use of decoupled row and column sub-crossbar modules in combination with feeder wiring and control logic that enables routing between ports on the row and column sub-crossbar modules. The corresponding MoDe-X router supports 5-port routing between various router input and output port combinations while reducing both router area and power consumption when compared with a conventional 5×5 crossbar design and implementation. The MoDe-X micro-architecture can be configured to support both single and dual local port injection configurations.

    摘要翻译： 布局感知的模块化去耦交叉开关和路由器，用于片上互连和相关的微架构和操作方法。 公开了一种称为MoDe-X（模块化解耦交叉开关）的交叉开关和路由器架构，其支持用于2D网状互连的5端口路由，并且通过使用去耦的行和列子交叉模块与馈线布线和控制逻辑 这可以在行和列子交叉杆模块上的端口之间进行路由。 相应的MoDe-X路由器支持各种路由器输入和输出端口组合之间的5端口路由，与传统的5×5交叉开关设计和实现相比，可以减少路由器面积和功耗。 MoDe-X微架构可以配置为支持单端口和双端口注入配置。

    REGION BASED TECHNIQUE FOR ACCURATELY PREDICTING MEMORY ACCESSES
    10.
    发明申请
    REGION BASED TECHNIQUE FOR ACCURATELY PREDICTING MEMORY ACCESSES 有权
    准确预测存储器访问的基于区域的技术

    公开(公告)号：US20110320762A1

    公开(公告)日：2011-12-29

    申请号：US12821935

    申请日：2010-06-23

    申请人： Livio B. Soares ,  Naveen Cherukuri ,  Akhilesh Kumar ,  Mani Azimi

    发明人： Livio B. Soares ,  Naveen Cherukuri ,  Akhilesh Kumar ,  Mani Azimi

    IPC分类号： G06F12/10

    CPC分类号： G06F12/0862 ,  G06F12/10 ,  G06F12/1027 ,  G06F2212/6024

    摘要： In one embodiment, the present invention includes a processor comprising a page tracker buffer (PTB), the PTB including a plurality of entries to store an address to a cache page and to store a signature to track an access to each cache line of the cache page, and a PTB handler, the PTB handler to load entries into the PTB and to update the signature. Other embodiments are also described and claimed.

    摘要翻译： 在一个实施例中，本发明包括一个包括页面跟踪缓冲器（PTB）的处理器，该PTB包括多个条目以将地址存储到高速缓存页面并且存储签名以跟踪对高速缓存的每个高速缓存行的访问 页面和PTB处理程序，PTB处理程序将条目加载到PTB中并更新签名。 还描述和要求保护其他实施例。