发明申请
- 专利标题: Semiconductor testing equipment, testing method for semiconductor, fabrication method of semiconductor, and semiconductor memory
- 专利标题(中): 半导体测试设备,半导体测试方法,半导体制造方法和半导体存储器
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申请号: US11012355申请日: 2004-12-16
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公开(公告)号: US20050149803A1公开(公告)日: 2005-07-07
- 发明人: Katsunori Hirano , Shuji Kikuchi , Yuji Sonoda , Wen Li , Tadanobu Toba , Takashi Kanesaka , Masayuki Takahashi
- 申请人: Katsunori Hirano , Shuji Kikuchi , Yuji Sonoda , Wen Li , Tadanobu Toba , Takashi Kanesaka , Masayuki Takahashi
- 优先权: JP2003-419056 20031217
- 主分类号: G01R31/28
- IPC分类号: G01R31/28 ; G01R31/3183 ; G01R31/3193 ; G11C29/44 ; G11C29/56 ; G11C29/00 ; G06F11/00
摘要:
Semiconductor testing equipment according to the present invention comprises: an algorithmic pattern generator for generating a test pattern for testing a memory under test and applying the pattern to the memory under test; a comparator for comparing a response signal from the memory under test and an expected value from tho algorithmic pattern generator; a fail address acquisition part for storing an address of the memory under test (fail address) when a result compared by the comparator is failed; a fail address analysis part for analyzing the failed address and calculating the address to be repaired (repair address); and a cycle-pattern generator for redundancy processing for inserting the address to be repaired into a test pattern and applying the address to the memory under test, so that even when capacity of the semiconductor memory is increased, a fabrication yield thereof is raised by testing the memory after the packaging and by performing the redundancy processing of a defective.