公开(公告)号：US20080262760A1

公开(公告)日：2008-10-23

申请号：US12099868

申请日：2008-04-09

Applicant: Yuichi Sakurai ,  Tadanobu Toba ,  Shuji Kikuchi

Inventor： Yuichi Sakurai ,  Tadanobu Toba ,  Shuji Kikuchi

IPC: G01R31/303

CPC classification number: G06F13/4045 ,  G01N21/95684

Abstract: A semiconductor inspecting apparatus includes: a buffer memory whose width is matched to the greater of parallel bus width and the width of the number of serial lanes; a preceding stage bus switching unit that fills the buffer memory with input data without making a free space; equivalent transmission capacity conversion including a following stage bus switching unit that fills read data to the width of an arbitrary number of serial lanes without making a free space; a preceding stage bus switching unit that fills a buffer memory with input data without making a free space; and equivalent transmission capacity inverse conversion including a following stage bus switching unit that fills a parallel bus of arbitrary width with data read from a buffer memory without making a free space.

Abstract translation: 半导体检查装置包括：缓冲存储器，其宽度与并行总线宽度越大并且串行数量的宽度相匹配; 前级总线切换单元，其不输入空闲空间来填充缓冲存储器中的输入数据; 等效传输容量转换，包括后级总线切换单元，其将读取的数据填充到任意数量的串行通道的宽度而不产生空闲空间; 前级总线切换单元，其不输入空闲空间来填充具有输入数据的缓冲存储器; 以及等效传输容量逆变换，包括后级总线切换单元，其填充具有从缓冲存储器读取的数据的任意宽度的并行总线，而不产生空闲空间。

公开(公告)号：US07225372B2

公开(公告)日：2007-05-29

申请号：US10949192

申请日：2004-09-27

Applicant: Iwao Suzuki ,  Shuji Kikuchi ,  Fumie Kobayashi ,  Hideyuki Aoki

Inventor： Iwao Suzuki ,  Shuji Kikuchi ,  Fumie Kobayashi ,  Hideyuki Aoki

IPC: G11C29/00

CPC classification number: G11C29/56 ,  G11C29/10

Abstract: A testing circuit using ALPG is mounted in a testing board in which sockets for mounting semiconductor memories as devices to be tested in the board is mounted and a volatile memory for storing a data table for generating a random pattern is provided in the testing circuit so that a test using a test pattern having no regularity is performed using the data table in addition to a test using a test pattern having regularity generated by the ALPG.

Abstract translation: 使用ALPG的测试电路安装在测试板中，其中安装半导体存储器的插座作为板中要测试的器件，并且在测试电路中提供用于存储用于产生随机模式的数据表的易失性存储器，使得 除了使用由ALPG生成的规则性的测试图案的测试之外，还使用数据表来执行使用不规则的测试图案的测试。

公开(公告)号：US20070036421A1

公开(公告)日：2007-02-15

申请号：US11500979

申请日：2006-08-09

Applicant: Tadanobu Toba ,  Shuji Kikuchi ,  Yuichi Sakurai ,  Wen Li

Inventor： Tadanobu Toba ,  Shuji Kikuchi ,  Yuichi Sakurai ,  Wen Li

IPC: G06K9/00

CPC classification number: G06T7/0004 ,  G06T2207/30148

Abstract: When an inspection apparatus of a semiconductor device repeatedly executes computation of prescribed area data, such as image processing for detecting defects, procedures for commanding, data load, computation, and data store need to be repeated the number of times of the computation. This may impose a limitation on the speeding up of the operation. In addition, when performing parallel computation by a high-capacity image processing system for handling minute images, a lot of processors are needed, resulting in an increase in cost. In order to solve the above-mentioned problems, in the invention, an inspection apparatus of a semiconductor device includes a data memory including an access section which is capable of reading and writing simultaneously, a plurality of numerical computation units, a connector for connecting the data memory and the numerical computation units, a controller for collectively controlling the contents of processing by the plurality of numerical computation units, another connector for connecting the numerical computation units and the controller, and a data transfer controller for controlling data transfer between the numerical computation units.

Abstract translation: 当半导体装置的检查装置重复执行规定区域数据的计算时，例如用于检测缺陷的图像处理，命令，数据加载，计算和数据存储的过程需要重复计算次数。 这可能对操作的加速施加限制。 此外，当通过大容量图像处理系统执行并行计算以处理微小图像时，需要许多处理器，导致成本增加。 为了解决上述问题，在本发明中，半导体装置的检查装置包括数据存储器，该数据存储器包括能够同时读写的访问部分，多个数值计算单元，连接器 数据存储器和数值计算单元，用于共同控制多个数值计算单元的处理内容的控制器，用于连接数值计算单元和控制器的另一连接器，以及用于控制数值计算之间的数据传送的数据传输控制器 单位。

公开(公告)号：US20060239055A1

公开(公告)日：2006-10-26

申请号：US11378368

申请日：2006-03-20

Applicant: Yuji Sonoda ,  Shuji Kikuchi ,  Katsunori Hirano ,  Ichiro Anjo ,  Mitsuaki Katagiri

Inventor： Yuji Sonoda ,  Shuji Kikuchi ,  Katsunori Hirano ,  Ichiro Anjo ,  Mitsuaki Katagiri

IPC: G11C5/02

CPC classification number: G11C29/48 ,  G11C5/04 ,  G11C2029/2602 ,  G11C2029/5602

Abstract: The present invention relates to a DRAM stacked packages, a DIMM, a method for testing them, and a semiconductor manufacturing method. According to the present invention, there is provided a DRAM stacked package comprising: a plurality of stacked DRAMs; external terminals to which test equipment is connected, said external terminals being used to input/output at least address, command, and data; and an interface chip provided between said plurality of stacked DRAMs and said external terminals. The plurality of DRAMs and the interface chip are implemented on a package. The interface chip comprises: a test circuit including: an algorithmic pattern generator for generating a test pattern used to test the plurality of DRAMs; applying circuits for applying said generated test pattern to the plurality of DRAMs; and a comparator for comparing each response signal received from the plurality of DRAMs with an expected value for judgment.

公开(公告)号：US20060164115A1

公开(公告)日：2006-07-27

申请号：US10533127

申请日：2003-10-29

Applicant: Yasumaro Komiya ,  Shuji Kikuchi ,  Koichi Uesaka ,  Tadanobu Toba ,  Keiichi Yamamoto

Inventor： Yasumaro Komiya ,  Shuji Kikuchi ,  Koichi Uesaka ,  Tadanobu Toba ,  Keiichi Yamamoto

IPC: G01R31/26

CPC classification number: G01R31/311

Abstract: The present invention aims at performing a semiconductor integrated circuit defect analysis with a simplified analysis apparatus and simplifying a defect analysis work. A defect analysis apparatus for a semiconductor integrated circuit is characterized in that a presence/absence of a defect is detected by irradiating an electromagnetic field from a probe to the semiconductor integrated circuit and detecting an electric characteristic variation such as a power supply current variation in the semiconductor integrated circuit.

Abstract translation: 本发明旨在利用简化的分析装置进行半导体集成电路缺陷分析，并简化缺陷分析工作。 半导体集成电路的缺陷分析装置的特征在于，通过将来自探针的电磁场照射到半导体集成电路来检测缺陷的存在/不存在，并且检测诸如电源电流变化的电特性变化 半导体集成电路。

公开(公告)号：US20050044458A1

公开(公告)日：2005-02-24

申请号：US10949192

申请日：2004-09-27

Applicant: Iwao Suzuki ,  Shuji Kikuchi ,  Fumie Kobayashi ,  Hideyuki Aoki

Inventor： Iwao Suzuki ,  Shuji Kikuchi ,  Fumie Kobayashi ,  Hideyuki Aoki

IPC: G01R31/30 ,  G01R31/28 ,  G01R31/3183 ,  G11C29/10 ,  G11C29/56 ,  G11C7/00 ,  G11C29/00

CPC classification number: G11C29/56 ,  G11C29/10

Abstract: A testing circuit using ALPG is mounted in a testing board in which sockets for mounting semiconductor memories as devices to be tested in the board is mounted and a volatile memory for storing a data table for generating a random pattern is provided in the testing circuit so that a test using a test pattern having no regularity is performed using the data table in addition to a test using a test pattern having regularity generated by the ALPG.

Abstract translation: 使用ALPG的测试电路安装在测试板中，其中安装半导体存储器的插座作为板中要测试的器件，并且在测试电路中提供用于存储用于产生随机模式的数据表的易失性存储器，使得 除了使用由ALPG生成的规则性的测试图案的测试之外，还使用数据表来执行使用不规则的测试图案的测试。

公开(公告)号：US5089710A

公开(公告)日：1992-02-18

申请号：US577001

申请日：1990-09-04

Applicant: Shuji Kikuchi ,  Mitsuyuki Yamaguchi ,  Masahiko Matsudo

Inventor： Shuji Kikuchi ,  Mitsuyuki Yamaguchi ,  Masahiko Matsudo

IPC: H01J37/317 ,  H01J37/02 ,  H01L21/265

CPC classification number: H01J37/026

Abstract: An ion implantation equipment for implanting ion beam into an implanting target characterized in that an electrons are induced to the direction of an ion beam being injected to said implanting target, and a predetermined bias voltage is applied between a plasma generation chamber and Faraday.

公开(公告)号：US4905183A

公开(公告)日：1990-02-27

申请号：US78993

申请日：1987-07-29

Applicant: Ikuo Kawaguchi ,  Shuji Kikuchi ,  Chisato Hamabe

Inventor： Ikuo Kawaguchi ,  Shuji Kikuchi ,  Chisato Hamabe

IPC: G01R31/319 ,  G06F7/544

CPC classification number: G06F7/544 ,  G01R31/31921

Abstract: A pattern generator permitting to output patterns at high speed and having an operating function, which is suitable for generating test patterns for memory ICs. Although it was known heretofore to increase the operating speed by operating a plurality of pattern generators, for which patterns were generated from memories, in which patterns were previously stored, in parallel, it was not possible to operate pattern generators having an operating function in parallel. A method, by which the order of execution of operation processing instructions is assigned to each of the pattern generators and operation processing instructions are accumulated and allows patterns to be generated at high speed by means of a pattern generator having an operating function. Specifically, the operating processing instructions are grouped and rearranged such that all the pattern generators execute instructions in parallel.

Abstract translation: 模式发生器允许高速输出图形并具有适用于产生存储器IC的测试图案的操作功能。 虽然迄今为止已知通过操作多个图案发生器来提高操作速度，对于哪些图案从先前存储图案的存储器生成的图案并行地，不可能并行地操作具有操作功能的图案生成器 。 通过这样一种方法，通过这种方式，对每个模式发生器和操作处理指令分配操作处理指令的执行顺序，并且通过具有操作功能的模式发生器允许高速生成模式。 具体地，操作处理指令被分组和重新排列，使得所有模式发生器并行地执行指令。

公开(公告)号：US4783597A

公开(公告)日：1988-11-08

申请号：US924370

申请日：1986-10-29

Applicant: Hisanori Misawa ,  Hidetaro Nishimura ,  Takaya Tsujimaru ,  Shuji Kikuchi ,  Nobuyuki Abe ,  Kouichi Mori

Inventor： Hisanori Misawa ,  Hidetaro Nishimura ,  Takaya Tsujimaru ,  Shuji Kikuchi ,  Nobuyuki Abe ,  Kouichi Mori

IPC: H01L21/265 ,  H01J37/02 ,  H01J37/317

CPC classification number: H01J37/026 ,  H01J37/3171

Abstract: An ion implant apparatus which forms ions from an ion source into an ion beam to implant the ions into a target to be ion-implanted through an ion beam introduction tube. The ion implant apparatus comprises: radiation means for radiating an electron beam, the radiating means fixed on the ion beam introduction tube; and a target for being radiated by an electron beam, said target reflecting the electron beam to generate a reflectance beam, the electron beam causing a secondary electron beam to be emitted from the electron beam target, the electron beam target being formed so as to prevent the reflectance beam and the secondary electron beam from being directly radiated on the target to be ion-implanted. The apparatus can keep high energy electrons from the surface of a wafer thereby to prevent the wafer from being charged negatively, and can trap the high energy electrons in the measuring system thereby to decrease errors in measuring a number of dopant atoms.

Abstract translation: 一种离子注入装置，其从离子源形成离子到离子束中，以将离子注入到通过离子束引入管离子注入的靶中。 离子注入装置包括：用于辐射电子束的辐射装置，固定在离子束引入管上的辐射装置; 以及通过电子束照射的目标，所述目标反射电子束以产生反射光束，使得从电子束靶发射二次电子束的电子束，形成电子束靶，以防止 反射光束和二次电子束直接照射在待离子注入的靶上。 该装置可以保持来自晶片表面的高能电子，从而防止晶片被负电荷捕获，并且可以捕获测量系统中的高能电子，从而减少测量多个掺杂原子的误差。

公开(公告)号：US08653458B2

公开(公告)日：2014-02-18

申请号：US13812121

申请日：2011-06-22

Applicant: Yoshiro Gunji ,  Shuji Kikuchi

Inventor： Yoshiro Gunji ,  Shuji Kikuchi

IPC: G01N23/00

CPC classification number: H01J37/261 ,  H01J37/1474 ,  H01J37/265 ,  H01J37/28

Abstract: An inspection device carries out beam scanning on a stable scanning cycle by enabling flexible change of various scanning sequences according to inspection conditions thereof, and at the same time, eliminates as much unevenness as possible in scanning cycle which hinders stabilization of charging. A beam scanning scheduler schedules beam scanning based on an inputted scanning condition, and a programmable sequencer carries out beam scanning control according to a beam scanning schedule generated by the beam scanning scheduler. The scanning scheduler calculates scanning line reference coordinates on a scanning-line-by-scanning-line basis, based on the scanning condition, and issues a scanning cycle trigger. The programmable sequencer controls supply timing of the scanning line reference coordinates and a scanning position on an in-line pixel-by-pixel basis, based on line scanning procedure information and the scanning cycle trigger provided from the beam scanning scheduler.

Abstract translation: 检查装置通过根据其检查条件灵活地改变各种扫描序列，在稳定的扫描周期进行光束扫描，并且同时消除了妨碍充电稳定性的扫描周期中尽可能多的不均匀性。 光束扫描调度器基于输入的扫描条件调度波束扫描，并且可编程序定序器根据由波束扫描调度器生成的波束扫描调度执行波束扫描控制。 扫描调度器基于扫描条件在逐行扫描线上计算扫描线参考坐标，并发出扫描周期触发。 基于行扫描程序信息和从波束扫描调度器提供的扫描周期触发，可编程序器根据逐行逐像素地控制扫描线参考坐标的提供定时和扫描位置。