发明申请
- 专利标题: Pattern verification method, pattern verification system, mask manufacturing method and semiconductor device manufacturing method
- 专利标题(中): 模式验证方法,模式验证系统,掩模制造方法和半导体器件制造方法
-
申请号: US11012494申请日: 2004-12-16
-
公开(公告)号: US20050153217A1公开(公告)日: 2005-07-14
- 发明人: Kyoko Izuha , Shigeki Nojima , Toshiya Kotani , Satoshi Tanaka
- 申请人: Kyoko Izuha , Shigeki Nojima , Toshiya Kotani , Satoshi Tanaka
- 优先权: JP2003-421349 20031218
- 主分类号: G03F1/36
- IPC分类号: G03F1/36 ; G03F1/68 ; G03F1/70 ; G03F7/20 ; G03F9/00 ; G06F17/50 ; H01L21/027
摘要:
A pattern verification method comprising preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a variable range for each of the process parameters, computing a positional displacement for each first points corresponding to the evaluation point, first points computed using correction mask pattern and a plurality of combinations of parameter values obtained by varying the process parameters within the variable range or within the respective variable ranges, the positional displacement being displacement between first point and the evaluation point, computing a statistics of the positional displacements for each of the evaluation points, and outputting information modifying the mask pattern according to the statistics.
公开/授权文献
- US07571417B2 Method and system for correcting a mask pattern design 公开/授权日:2009-08-04
信息查询