发明申请
US20050153497A1 Method of forming a FET having ultra-low on-resistance and low gate charge
有权
形成具有超低导通电阻和低栅极电荷的FET的方法
- 专利标题： Method of forming a FET having ultra-low on-resistance and low gate charge
- 专利标题（中）： 形成具有超低导通电阻和低栅极电荷的FET的方法
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申请号： US10997818申请日： 2004-11-24
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公开(公告)号： US20050153497A1公开(公告)日： 2005-07-14
- 发明人: Izak Bencuya , Brian Mo , Ashok Challa
- 申请人： Izak Bencuya , Brian Mo , Ashok Challa
- 主分类号： H01L21/336
- IPC分类号： H01L21/336 ; H01L29/08 ; H01L29/423 ; H01L29/78 ; H01L21/8234
摘要：
In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.