公开(公告)号：US20050153497A1

公开(公告)日：2005-07-14

申请号：US10997818

申请日：2004-11-24

申请人： Izak Bencuya ,  Brian Mo ,  Ashok Challa

发明人： Izak Bencuya ,  Brian Mo ,  Ashok Challa

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/42368

摘要： In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.

摘要翻译： 根据本发明的示例性实施例，提供了第一导电型硅的衬底。 形成第一导电型硅的衬底帽区域，使得在衬底帽区域和衬底之间形成结。 形成第二导电型硅的体区，使得在体区和衬底帽区之间形成接合部。 然后形成至少延伸穿过身体区域的沟槽。 然后在身体区域的上部形成第一导电类型的源极区域。 作为一个或多个温度循环的结果，第一导电类型的扩散区形成在体区的下部，使得源极区域和外扩散区域之间的间隔限定了场的沟道长度 效应晶体管。

公开(公告)号：US06696726B1

公开(公告)日：2004-02-24

申请号：US09640955

申请日：2000-08-16

申请人： Izak Bencuya ,  Brian Sze-Ki Mo ,  Ashok Challa

发明人： Izak Bencuya ,  Brian Sze-Ki Mo ,  Ashok Challa

IPC分类号： H01L2976

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368

摘要： A vertical trench double-diffused metal-oxide-semiconductor (DMOS) field effect transistor characterized by a reduced drain-to-source resistance and a lower gate charge and providing a high transconductance and an enhanced frequency response.

摘要翻译： 垂直沟槽双扩散金属氧化物半导体（DMOS）场效应晶体管，其特征在于降低的漏极 - 源极电阻和较低的栅极电荷，并提供高跨导和增强的频率响应。

公开(公告)号：US08710584B2

公开(公告)日：2014-04-29

申请号：US13344269

申请日：2012-01-05

申请人： Izak Bencuya ,  Brian Sze-Ki Mo ,  Ashok Challa

发明人： Izak Bencuya ,  Brian Sze-Ki Mo ,  Ashok Challa

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/42368

摘要： A metal-oxide-semiconductor field effect transistor (MOSFET) includes a substrate, the substrate being heavily doped and of a first conductivity type, a substrate cap region disposed on the substrate, the substrate cap region being heavily doped and of the first conductivity type and a body region disposed on the substrate cap region, the body region being lightly doped and of a second conductivity type. The MOSFET also includes a trench extending into the body region, a source region of the first conductivity type disposed in the body region and in contact with an upper portion of a sidewall of the trench and an out-diffusion region of the first conductivity type formed such that a spacing between the source region and the out-diffusion region defines a channel region of the MOSFET extending along the sidewall of the trench.

摘要翻译： 金属氧化物半导体场效应晶体管（MOSFET）包括衬底，衬底被重掺杂并具有第一导电类型，衬底帽区域设置在衬底上，衬底帽区域被重掺杂并且具有第一导电类型 以及设置在所述基板盖区域上的主体区域，所述主体区域被轻掺杂并具有第二导电类型。 MOSFET还包括延伸到体区的沟槽，设置在体区中并与沟槽的侧壁的上部接触的第一导电类型的源区和形成的第一导电类型的扩散区 使得源极区域和外扩散区域之间的间隔限定沿着沟槽的侧壁延伸的MOSFET的沟道区域。

公开(公告)号：US20120171828A1

公开(公告)日：2012-07-05

申请号：US13344269

申请日：2012-01-05

申请人： Izak Bencuya ,  Brian Sze-Ki Mo ,  Ashok Challa

发明人： Izak Bencuya ,  Brian Sze-Ki Mo ,  Ashok Challa

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/42368

摘要： In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.

摘要翻译： 根据本发明的示例性实施例，提供了第一导电型硅的衬底。 形成第一导电型硅的衬底帽区域，使得在衬底帽区域和衬底之间形成结。 形成第二导电型硅的体区，使得在体区和衬底帽区之间形成接合部。 然后形成至少延伸穿过身体区域的沟槽。 然后在身体区域的上部形成第一导电类型的源极区域。 作为一个或多个温度循环的结果，第一导电类型的扩散区形成在体区的下部，使得源极区域和外扩散区域之间的间隔限定了场的沟道长度 效应晶体管。

公开(公告)号：US08101484B2

公开(公告)日：2012-01-24

申请号：US12821590

申请日：2010-06-23

申请人： Izak Bencuya ,  Brian Sze-Ki Mo ,  Ashok Challa

发明人： Izak Bencuya ,  Brian Sze-Ki Mo ,  Ashok Challa

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/42368

摘要： In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.

摘要翻译： 根据本发明的示例性实施例，提供了第一导电型硅的衬底。 形成第一导电型硅的衬底帽区域，使得在衬底帽区域和衬底之间形成结。 形成第二导电型硅的体区，使得在体区和衬底帽区之间形成接合部。 然后形成至少延伸穿过身体区域的沟槽。 然后在身体区域的上部形成第一导电类型的源极区域。 作为一个或多个温度循环的结果，第一导电类型的扩散区形成在体区的下部，使得源极区域和外扩散区域之间的间隔限定了场的沟道长度 效应晶体管。

公开(公告)号：US20100258864A1

公开(公告)日：2010-10-14

申请号：US12821590

申请日：2010-06-23

申请人： Izak Bencuya ,  Brian Sze-Ki Mo ,  Ashok Challa

发明人： Izak Bencuya ,  Brian Sze-Ki Mo ,  Ashok Challa

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/42368

摘要： In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.

摘要翻译： 根据本发明的示例性实施例，提供了第一导电型硅的衬底。 形成第一导电型硅的衬底帽区域，使得在衬底帽区域和衬底之间形成结。 形成第二导电型硅的体区，使得在体区和衬底帽区之间形成接合部。 然后形成至少延伸穿过身体区域的沟槽。 然后在身体区域的上部形成第一导电类型的源极区域。 作为一个或多个温度循环的结果，第一导电类型的扩散区形成在体区的下部，使得源极区域和外扩散区域之间的间隔限定了场的沟道长度 效应晶体管。

公开(公告)号：US07745289B2

公开(公告)日：2010-06-29

申请号：US10997818

申请日：2004-11-24

申请人： Izak Bencuya ,  Brian Sze-Ki Mo ,  Ashok Challa

发明人： Izak Bencuya ,  Brian Sze-Ki Mo ,  Ashok Challa

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/42368

摘要： In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.

摘要翻译： 根据本发明的示例性实施例，提供了第一导电型硅的衬底。 形成第一导电型硅的衬底帽区域，使得在衬底帽区域和衬底之间形成结。 形成第二导电型硅的体区，使得在体区和衬底帽区之间形成接合部。 然后形成至少延伸穿过身体区域的沟槽。 然后在身体区域的上部形成第一导电类型的源极区域。 作为一个或多个温度循环的结果，第一导电类型的扩散区形成在体区的下部，使得源极区域和外扩散区域之间的间隔限定了场的沟道长度 效应晶体管。

公开(公告)号：US08304829B2

公开(公告)日：2012-11-06

申请号：US12408552

申请日：2009-03-20

申请人： Joseph A. Yedinak ,  Ashok Challa

发明人： Joseph A. Yedinak ,  Ashok Challa

IPC分类号： H01L29/66

CPC分类号： H01L29/0634 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/872 ,  H01L29/8725

摘要： Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

公开(公告)号：US20110303975A1

公开(公告)日：2011-12-15

申请号：US13152041

申请日：2011-06-02

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.

摘要翻译： 场效应晶体管包括延伸到第一导电类型的半导体区域的多个沟槽。 多个沟槽包括多个门控沟槽和多个非门控沟槽。 第二导电体的主体区域在相邻沟槽之间的半导体区域中延伸。 电介质材料填充每个门控沟槽和非门控沟槽的底部。 栅极电极设置在每个门控沟槽中。 第二导电类型的导电材料设置在每个非门控沟槽中，使得导电材料并且沿着非门控沟槽的侧壁接触对应的主体区域。

公开(公告)号：US20100308402A1

公开(公告)日：2010-12-09

申请号：US12480065

申请日：2009-06-08

申请人： Suku Kim ,  Dan Calafut ,  Ihsiu Ho ,  Dan Kinzer ,  Steven Sapp ,  Ashok Challa ,  Seokjin Jo ,  Mark Larsen

发明人： Suku Kim ,  Dan Calafut ,  Ihsiu Ho ,  Dan Kinzer ,  Steven Sapp ,  Ashok Challa ,  Seokjin Jo ,  Mark Larsen

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0865 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4933

摘要： Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.

摘要翻译： 描述了用于制造包含3D通道架构的这种设备的半导体器件和方法。 3D通道架构使用双沟槽结构形成，该双沟槽结构包含多个下沟槽，该多个下沟槽在x和y定向沟槽中延伸并且被台面和上部沟槽隔开，该沟槽沿ay方向延伸并且位于基板的上部附近 源区。 因此，在主线状沟槽内形成较小的支柱沟槽。 这种架构产生基本垂直于常规线形通道排列的附加通道区域。 常规和垂直的通道区域通过其角部和顶部区域电连接以在所有三维空间中产生更高的电流。 通过这样的结构，半导体器件可以获得更高的沟道密度，更强的反转层和更均匀的阈值分布。 描述其他实施例。