发明申请
US20050230716A1 Semiconductor integrated circuit equipment and its manufacture method
审中-公开
半导体集成电路设备及其制造方法
- 专利标题： Semiconductor integrated circuit equipment and its manufacture method
- 专利标题（中）： 半导体集成电路设备及其制造方法
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申请号： US11107888申请日： 2005-04-18
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公开(公告)号： US20050230716A1公开(公告)日： 2005-10-20
- 发明人: Satoshi Moriya , Toshiyuki Kikuchi , Akihiko Konno , Hidenori Sato , Naoki Yamamoto , Masamichi Matsuoka , Hiraku Chakihara , Akio Nishida
- 申请人： Satoshi Moriya , Toshiyuki Kikuchi , Akihiko Konno , Hidenori Sato , Naoki Yamamoto , Masamichi Matsuoka , Hiraku Chakihara , Akio Nishida
- 专利权人： Renesas Technology Corp.
- 当前专利权人： Renesas Technology Corp.
- 优先权： JP2004-122428 20040419
- 主分类号： H01L23/522
- IPC分类号： H01L23/522 ; H01L21/336 ; H01L21/768 ; H01L21/8234 ; H01L21/8244 ; H01L27/088 ; H01L27/092 ; H01L27/11 ; H01L29/76
摘要：
The object of the present invention is to suppress the increase of the contact resistance at the interface between the metal layer and the silicon plug in the wiring structure in which a metal layer is formed on and connected to a silicon plug. For its achievement, a lower semiconductor layer (drain) of a vertical-type MISFET is connected to an intermediate metal layer via an underlying plug composed of a polycrystalline silicon film, and a trap layer composed of a silicon nitride (TiN) film is formed on a part of the surface of the intermediate metal layer so as to surround the plug. The trap layer is formed in order to prevent an undesired high-resistance oxide layer from being formed at the interface between the plug and the intermediate metal layer.
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