公开(公告)号：US20050230716A1

公开(公告)日：2005-10-20

申请号：US11107888

申请日：2005-04-18

申请人： Satoshi Moriya ,  Toshiyuki Kikuchi ,  Akihiko Konno ,  Hidenori Sato ,  Naoki Yamamoto ,  Masamichi Matsuoka ,  Hiraku Chakihara ,  Akio Nishida

发明人： Satoshi Moriya ,  Toshiyuki Kikuchi ,  Akihiko Konno ,  Hidenori Sato ,  Naoki Yamamoto ,  Masamichi Matsuoka ,  Hiraku Chakihara ,  Akio Nishida

IPC分类号： H01L23/522 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/088 ,  H01L27/092 ,  H01L27/11 ,  H01L29/76

CPC分类号： H01L27/11 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/092 ,  H01L29/6656

摘要： The object of the present invention is to suppress the increase of the contact resistance at the interface between the metal layer and the silicon plug in the wiring structure in which a metal layer is formed on and connected to a silicon plug. For its achievement, a lower semiconductor layer (drain) of a vertical-type MISFET is connected to an intermediate metal layer via an underlying plug composed of a polycrystalline silicon film, and a trap layer composed of a silicon nitride (TiN) film is formed on a part of the surface of the intermediate metal layer so as to surround the plug. The trap layer is formed in order to prevent an undesired high-resistance oxide layer from being formed at the interface between the plug and the intermediate metal layer.

摘要翻译： 本发明的目的是为了抑制金属层与硅插头之间的界面处的接触电阻的增加，其中形成金属层并连接到硅插头的布线结构中。 为了实现，垂直型MISFET的下半导体层（漏极）经由由多晶硅膜构成的下面的插塞连接到中间金属层，并且形成由氮化硅（TiN）膜构成的捕获层 在中间金属层的表面的一部分上，以围绕塞子。 形成陷阱层以防止在插塞和中间金属层之间的界面处形成不期望的高电阻氧化物层。

公开(公告)号：US08354730B2

公开(公告)日：2013-01-15

申请号：US11997436

申请日：2006-08-25

申请人： Satoshi Moriya ,  Toshio Saito ,  Goichi Yokoyama ,  Tsuyoshi Fujiwara ,  Hidenori Sato ,  Nobuaki Miyakawa

发明人： Satoshi Moriya ,  Toshio Saito ,  Goichi Yokoyama ,  Tsuyoshi Fujiwara ,  Hidenori Sato ,  Nobuaki Miyakawa

IPC分类号： H01L21/70

CPC分类号： H01L21/76898 ,  H01L21/2007 ,  H01L21/76232 ,  H01L21/8221 ,  H01L23/481 ,  H01L24/94 ,  H01L2224/2518 ,  H01L2924/01004 ,  H01L2924/04941 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/00

摘要： A structure obtaining a desired integrated circuit by sticking together a plurality of semiconductor substrates and electrically connecting integrated circuits formed on semiconductor chips of the respective semiconductor substrates is provided, and a penetrating electrode penetrating between a main surface and a rear surface of each of the semiconductor substrates and a penetrating separation portion separating the penetrating electrode are separately arranged. Thereby, after forming an insulation trench portion for formation of the penetrating separation portion on the semiconductor substrate, a MIS•FET is formed, and then, a conductive trench portion for formation of the penetrating electrode can be formed. Therefore, element characteristics of a semiconductor device having a three-dimensional structure can be improved.

摘要翻译： 提供了通过将形成在各个半导体衬底的半导体芯片上的多个半导体衬底和电连接集成电路粘合在一起而获得所需集成电路的结构，并且穿透电极穿透每个半导体衬底的主表面和后表面 分离基板和分离穿透电极的穿透分离部分。 因此，在半导体衬底上形成用于形成穿透分离部分的绝缘沟槽部分之后，形成MIS·FET，然后形成用于形成穿透电极的导电沟槽部分。 因此，可以提高具有三维结构的半导体器件的元件特性。

公开(公告)号：US20100090307A1

公开(公告)日：2010-04-15

申请号：US11997436

申请日：2006-08-25

申请人： Satoshi Moriya ,  Toshio Saito ,  Goichi Yokoyama ,  Tsuyoshi Fujiwara ,  Hidenori Sato ,  Nobuaki Miyakawa

发明人： Satoshi Moriya ,  Toshio Saito ,  Goichi Yokoyama ,  Tsuyoshi Fujiwara ,  Hidenori Sato ,  Nobuaki Miyakawa

IPC分类号： H01L29/06 ,  H01L21/76

CPC分类号： H01L21/76898 ,  H01L21/2007 ,  H01L21/76232 ,  H01L21/8221 ,  H01L23/481 ,  H01L24/94 ,  H01L2224/2518 ,  H01L2924/01004 ,  H01L2924/04941 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/00

摘要： A structure obtaining a desired integrated circuit by sticking together a plurality of semiconductor substrates and electrically connecting integrated circuits formed on semiconductor chips of the respective semiconductor substrates is provided, and a penetrating electrode penetrating between a main surface and a rear surface of each of the semiconductor substrates and a penetrating separation portion separating the penetrating electrode are separately arranged. Thereby, after forming an insulation trench portion for formation of the penetrating separation portion on the semiconductor substrate, a MIS·FET is formed, and then, a conductive trench portion for formation of the penetrating electrode can be formed. Therefore, element characteristics of a semiconductor device having a three-dimensional structure can be improved.

摘要翻译： 提供了通过将形成在各个半导体衬底的半导体芯片上的多个半导体衬底和电连接集成电路粘合在一起而获得所需集成电路的结构，并且穿透电极穿透每个半导体衬底的主表面和后表面 分离基板和分离穿透电极的穿透分离部分。 因此，在半导体衬底上形成用于形成穿透分离部分的绝缘沟槽部分之后，形成MIS·FET，然后形成用于形成穿透电极的导电沟槽部分。 因此，可以提高具有三维结构的半导体器件的元件特性。

公开(公告)号：US07948088B2

公开(公告)日：2011-05-24

申请号：US12063606

申请日：2006-08-25

申请人： Toshio Saito ,  Satoshi Moriya ,  Morio Nakamura ,  Goichi Yokoyama ,  Tatsuyuki Saito ,  Nobuaki Miyakawa

发明人： Toshio Saito ,  Satoshi Moriya ,  Morio Nakamura ,  Goichi Yokoyama ,  Tatsuyuki Saito ,  Nobuaki Miyakawa

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L21/763 ,  H01L21/76898 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/45 ,  H01L24/48 ,  H01L25/50 ,  H01L27/0203 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： In order to improve the manufacturing yield of a semiconductor device having a three-dimensional structure in which a plurality of chips are stacked and attached to each other, the opening shape of each of conductive grooves (4A) formed in each chip (C2) obtained from a wafer (W2) is rectangular, and the number of the conductive grooves (4A) whose long-sides are directed in a Y direction and the number of the conductive grooves (4A) whose long-sides are directed in an X direction perpendicular to the Y direction are made to be approximately equal to each other number in the entire wafer (W2), whereby the film stress upon embedding of a conductive film into the interior of the conductive grooves is reduced, and generation of exfoliation and micro-cracks in the conductive film or warpage and cracks of the wafer (W2) are prevented.

摘要翻译： 为了提高具有多个芯片彼此堆叠并附接的三维结构的半导体器件的制造成品，形成在每个芯片（C2）中的每个导电槽（4A）的开口形状获得 从晶片（W2）的长方形的长方形的导体槽（4A）的长度方向的长度方向的数量和长边方向的X方向的导体槽的数量 使整个晶片（W2）的Y方向大致相等，由此导电膜嵌入导电槽内的膜应力减小，剥离和微裂纹的产生 导致膜或翘曲和晶片（W2）的裂纹被阻止。

公开(公告)号：US20090174080A1

公开(公告)日：2009-07-09

申请号：US12063606

申请日：2006-08-25

申请人： Toshio Saito ,  Satoshi Moriya ,  Morio Nakamura ,  Goichi Yokoyama ,  Tatsuyuki Saito ,  Nobuaki Miyakawa

发明人： Toshio Saito ,  Satoshi Moriya ,  Morio Nakamura ,  Goichi Yokoyama ,  Tatsuyuki Saito ,  Nobuaki Miyakawa

IPC分类号： H01L23/522

CPC分类号： H01L25/0657 ,  H01L21/763 ,  H01L21/76898 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/45 ,  H01L24/48 ,  H01L25/50 ,  H01L27/0203 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： In order to improve the manufacturing yield of a semiconductor device having a three-dimensional structure in which a plurality of chips are stacked and attached to each other, the opening shape of each of conductive grooves (4A) formed in each chip (C2) obtained from a wafer (W2) is rectangular, and the number of the conductive grooves (4A) whose long-sides are directed in a Y direction and the number of the conductive grooves (4A) whose long-sides are directed in an X direction perpendicular to the Y direction are made to be approximately equal to each other number in the entire wafer (W2), whereby the film stress upon embedding of a conductive film into the interior of the conductive grooves is reduced, and generation of exfoliation and micro-cracks in the conductive film or warpage and cracks of the wafer (W2) are prevented.

摘要翻译： 为了提高具有多个芯片彼此堆叠并附接的三维结构的半导体器件的制造成品，形成在每个芯片（C2）中的每个导电槽（4A）的开口形状获得 从晶片（W2）的长方形的长方形的导体槽（4A）的长度方向的长度方向的数量和长边方向的X方向的导体槽的数量 使整个晶片（W2）的Y方向大致相等，由此导电膜嵌入导电槽内的膜应力减小，剥离和微裂纹的产生 导致膜或翘曲和晶片（W2）的裂纹被阻止。

公开(公告)号：US07238296B2

公开(公告)日：2007-07-03

申请号：US10646805

申请日：2003-08-25

申请人： Satoshi Moriya

发明人： Satoshi Moriya

IPC分类号： H01C7/00 ,  H01C3/00 ,  C22C9/05

CPC分类号： H01B3/004 ,  H01B1/02 ,  H01C7/06 ,  H01C17/06553

摘要： When the entire amount of conductive metal mixed powder made of copper, manganese, and germanium is 100 parts by weight, the metal mixed powder is formed by mixing 4.0 to 13.0 parts manganese by weight, 0.2 to 1.4 parts germanium by weight, and 85.6 to 95.8 parts copper by weight, and 0 to 10 parts glass powder by weight and 0 to 10 parts copper-oxide powder by weight are mixed relative to the entire amount (100 parts by weight) of these metal components. The obtained resistive paste is then baked, and the resistive composition having the low resistance value and low TCR may be obtained. In addition, a resistor is made by forming the resistive element upon a substrate.

摘要翻译： 当由铜，锰和锗制成的导电金属混合粉末的总量为100重量份时，通过将4.0〜13.0重量％的锰，0.2〜1.4重量％的锗和85.6重量％ 相对于这些金属成分的总量（100重量份），将95.8重量份的铜和0-10重量份的玻璃粉末和0-10重量份的氧化铜粉末进行混合。 然后将获得的电阻浆料烘烤，并且可以获得具有低电阻值和低TCR的电阻组合物。 此外，通过在基板上形成电阻元件来制造电阻器。

公开(公告)号：US20060158304A1

公开(公告)日：2006-07-20

申请号：US10538744

申请日：2003-12-15

申请人： Satoshi Moriya

发明人： Satoshi Moriya

IPC分类号： H01C7/10

CPC分类号： C08K3/40 ,  C08K3/08 ,  C08K3/22 ,  H01C7/06 ,  H01C17/06526

摘要： A resistive material containing metallic powder including copper, manganese, and aluminum, glass powder and/ or copper oxide powder, and a vehicle is provided. The metallic powder is made by mixing 80 to 85 weight percent copper, 8 to 16 weight percent manganese, and 2 to 7 weight percent aluminum. A maximum of 10 weight percent glass powder and/ or copper oxide powder and 10 to 15 weight percent vehicle relative to the entire 100 weight percent metal mixed powder are added. The resulting resistive material is then wintered in an inactive atmosphere, thereby providing a resistor and a resistive element having target characteristics such as a low resistance, a low TCR value, and a low thermo-electromotive force.

摘要翻译： 提供了包含铜，锰和铝的金属粉末，玻璃粉末和/或氧化铜粉末和车辆的电阻材料。 金属粉末通过混合80至85重量％的铜，8至16重量％的锰和2至7重量％的铝来制备。 添加最多10重量％的玻璃粉末和/或氧化铜粉末和10至15重量％的载体相对于整个100重量％的金属混合粉末。 然后将所得到的电阻材料在无活性气氛中烧结，从而提供具有诸如低电阻，低TCR值和低热电动势的目标特性的电阻器和电阻元件。