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发明申请
US20050238129A1 False lock detection circuit and false lock detection method, PLL circuit and clock data recovery method, communication device and communication method, and optical disk reproducing device and optical disk reproducing method 失效
假锁检测电路和假锁检测方法，PLL电路和时钟数据恢复方法，通信装置和通信方法以及光盘再现装置和光盘再现方法

False lock detection circuit and false lock detection method, PLL circuit and clock data recovery method, communication device and communication method, and optical disk reproducing device and optical disk reproducing method
摘要：
Disclosed herein is a false lock detection circuit including: a data signal input section receiving an input of a data signal; a clock signal input section receiving an input of a clock signal generated from the data signal; a pattern detector obtaining the data signal on a basis of the clock signal, and detecting a data pattern in which adjacent pieces of data at at least three consecutive bits differ from each other; a phase period shift detector detecting a shift between periods of phases at a change point of the data signal and a change point of the clock signal; and a determining section determining whether a false lock has occurred on a basis of results of detection of the pattern detector and the phase period shift detector.
摘要（中）：

这里公开了一种假锁定检测电路，包括：数据信号输入部，接收数据信号的输入; 时钟信号输入部分，接收从数据信号产生的时钟信号的输入; 模式检测器基于时钟信号获取数据信号，并且检测其中至少三个连续位相邻的相邻数据段彼此不同的数据模式; 相位周期移位检测器，检测在数据信号的变化点和时钟信号的变化点的相位周期之间的偏移; 以及确定部，其基于图案检测器和相位周期移位检测器的检测结果来确定是否发生了假锁。

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