Test apparatus for testing an integrated circuit The invention relates to a test apparatus for testing an integrated circuit, particularly a DDR semiconductor memory, having at least one data connection for inputting at least one data signal, at least one DQS control connection for inputting at least one unaltered-frequency DQS signal, a device for phase shifting which is designed to take the unaltered-frequency DQS signal and produce a phase-shifted DQS signal, and a combinational logic device which is connected downstream of the device and which logically combines the unaltered-frequency DQS signal with the phase-shifted DQS signal to produce an altered-frequency DQS signal which has a frequency that is increased compared with the frequency of the unaltered-frequency DQS signal and which is provided for latching the data signals or as a clock signal. The invention also relates to a method for operating a test apparatus of this type.