Invention Application
US20050282392A1 STI FORMATION IN SEMICONDUCTOR DEVICE INCLUDING SOI AND BULK SILICON REGIONS
失效
在半导体器件中的STI形成,包括SOI和块状硅区域
- Patent Title: STI FORMATION IN SEMICONDUCTOR DEVICE INCLUDING SOI AND BULK SILICON REGIONS
- Patent Title (中): 在半导体器件中的STI形成,包括SOI和块状硅区域
-
Application No.: US10710060Application Date: 2004-06-16
-
Publication No.: US20050282392A1Publication Date: 2005-12-22
- Inventor: Michael Steigerwalt , Mahender Kumar , Herbert Ho , David Dobuzinsky , Johnathan Faltermeier , Denise Pendleton
- Applicant: Michael Steigerwalt , Mahender Kumar , Herbert Ho , David Dobuzinsky , Johnathan Faltermeier , Denise Pendleton
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Main IPC: H01L21/308
- IPC: H01L21/308 ; H01L21/311 ; H01L21/316 ; H01L21/762

Abstract:
Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.
Public/Granted literature
- US07118986B2 STI formation in semiconductor device including SOI and bulk silicon regions Public/Granted day:2006-10-10
Information query
IPC分类: