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    POLY FILLED SUBSTRATE CONTACT ON SOI STRUCTURE
    1.
    发明申请
    POLY FILLED SUBSTRATE CONTACT ON SOI STRUCTURE 失效
    多晶硅衬底接触SOI结构

    公开(公告)号：US20080113507A1

    公开(公告)日：2008-05-15

    申请号：US12014127

    申请日：2008-01-15

    Applicant: David Dobuzinsky ,  Byeong Kim ,  Effendi Leobandung ,  Munir Naeem ,  Brian Tessier

    Inventor： David Dobuzinsky ,  Byeong Kim ,  Effendi Leobandung ,  Munir Naeem ,  Brian Tessier

    IPC: H01L21/441

    CPC classification number: H01L21/84

    Abstract: Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.

    Abstract translation: 本文的实施方案提供了一种用于在SOI结构上形成多孔填充衬底接触的方法。 该方法在衬底上形成绝缘体，并在绝缘体内形成衬底接触孔。 绝缘子表面水平高于最终结构。 接下来，执行聚过填料，包括用多晶硅填充衬底接触孔并用多晶硅覆盖绝缘体。 具体地，多晶硅的厚度大于基板接触孔的尺寸。 接下来，蚀刻多晶硅，其中去除多晶硅的一部分，并且其中衬底接触孔部分地被多晶硅填充。 此外，多晶硅的蚀刻在多晶硅的顶部内形成凹形凹部。 所述多晶硅的蚀刻不与衬底接触。 绝缘体的过剩被抛光到所需的水平。

    STI FORMATION IN SEMICONDUCTOR DEVICE INCLUDING SOI AND BULK SILICON REGIONS
    2.
    发明申请
    STI FORMATION IN SEMICONDUCTOR DEVICE INCLUDING SOI AND BULK SILICON REGIONS 失效
    在半导体器件中的STI形成，包括SOI和块状硅区域

    公开(公告)号：US20050282392A1

    公开(公告)日：2005-12-22

    申请号：US10710060

    申请日：2004-06-16

    Applicant: Michael Steigerwalt ,  Mahender Kumar ,  Herbert Ho ,  David Dobuzinsky ,  Johnathan Faltermeier ,  Denise Pendleton

    Inventor： Michael Steigerwalt ,  Mahender Kumar ,  Herbert Ho ,  David Dobuzinsky ,  Johnathan Faltermeier ,  Denise Pendleton

    IPC: H01L21/308 ,  H01L21/311 ,  H01L21/316 ,  H01L21/762

    CPC classification number: H01L21/7624 ,  H01L21/3081 ,  H01L21/31612 ,  H01L21/76283

    Abstract: Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.

    Abstract translation: 公开了在绝缘体上硅（SOI）区域和体硅区域中形成或蚀刻硅沟槽隔离（STI）的方法以及如此形成的半导体器件。 可以通过使用STI掩模蚀刻到最上层的硅层，在SOI和体硅区域中同时蚀刻STI，进行蚀刻到体硅区域中期望的深度并停止在SOI区域的埋入绝缘体上的定时蚀刻 ，并蚀刻穿过SOI区域的埋层绝缘体。 用于该过程的掩埋绝缘体蚀刻可以以很少的复杂性作为硬掩模去除步骤的一部分来完成。 此外，通过为体区和SOI区域选择相同的深度，避免了后续CMP工艺的问题。 本发明还清除了可能存在氮化硅残留的SOI和体区之间的边界。

    VERTICAL SOI TRENCH SONOS CELL
    4.
    发明申请
    VERTICAL SOI TRENCH SONOS CELL 有权
    垂直SOI TRENCH SONOS电池

    公开(公告)号：US20070122971A1

    公开(公告)日：2007-05-31

    申请号：US11164513

    申请日：2005-11-28

    Applicant: David Dobuzinsky ,  Herbert Ho ,  Jack Mandelman ,  Yoichi Otani

    Inventor： David Dobuzinsky ,  Herbert Ho ,  Jack Mandelman ,  Yoichi Otani

    IPC: H01L21/336 ,  H01L27/12

    CPC classification number: H01L29/792 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7926

    Abstract: A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.

    Abstract translation: 提供一种半导体存储器件，其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元，其允许将致密的非易失性随机存取 基于SOI的互补金属氧化物半导体（CMOS）技术的存储器（NVRAM）单元。 使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。

    Method of improving etch uniformity in deep silicon etching
    6.
    发明授权
    Method of improving etch uniformity in deep silicon etching 失效
    提高深硅蚀刻蚀刻均匀性的方法

    公开(公告)号：US06806200B2

    公开(公告)日：2004-10-19

    申请号：US10291951

    申请日：2002-11-08

    Applicant: David Dobuzinsky ,  Siddhartha Panda ,  Rolf Weis ,  Richard Wise

    Inventor： David Dobuzinsky ,  Siddhartha Panda ,  Rolf Weis ,  Richard Wise

    IPC: H01L21302

    CPC classification number: H01L21/3065

    Abstract: A method is disclosed for improving etch uniformity in deep silicon etching of a monocrystalline silicon wafer. Such method includes forming a pad dielectric layer on a wafer including monocrystalline silicon, forming a silicon layer over the pad dielectric layer, and then applying a clamp to an edge of the wafer. The silicon layer is then removed except in areas protected by the clamp. Thereafter, a hardmask layer is applied and patterned on the wafer; and the wafer is then directionally etched with the patterned hardmask to etch trenches in the monocrystalline silicon. In such manner, a source of silicon (in the silicon layer) is provided at the wafer edge, such that the silicon loading is improved. In addition, the silicon layer at the wafer edge forms a blocking layer which prevents formation of black silicon.

    Abstract translation: 公开了一种用于改善单晶硅晶片的深硅蚀刻中的蚀刻均匀性的方法。 这种方法包括在包括单晶硅的晶片上形成焊盘电介质层，在焊盘介电层上形成硅层，然后在晶片的边缘上施加夹具。 然后除去在被夹具保护的区域之外除去硅层。 此后，将硬掩模层施加和图案化在晶片上; 然后用图案化的硬掩模对晶片进行定向蚀刻，以蚀刻单晶硅中的沟槽。以这种方式，在晶片边缘处提供硅源（在硅层中），使得硅负载得到改善。 此外，晶片边缘处的硅层形成防止形成黑色硅的阻挡层。

    STI FORMATION IN SEMICONDUCTOR DEVICE INCLUDING SOI AND BULK SILICON REGIONS
    7.
    发明申请
    STI FORMATION IN SEMICONDUCTOR DEVICE INCLUDING SOI AND BULK SILICON REGIONS 有权
    在半导体器件中的STI形成，包括SOI和块状硅区域

    公开(公告)号：US20060244093A1

    公开(公告)日：2006-11-02

    申请号：US11425467

    申请日：2006-06-21

    Applicant: Michael Steigerwalt ,  Mahender Kumar ,  Herbert Ho ,  David Dobuzinsky ,  Johnathan Faltermeier ,  Denise Pendleton

    Inventor： Michael Steigerwalt ,  Mahender Kumar ,  Herbert Ho ,  David Dobuzinsky ,  Johnathan Faltermeier ,  Denise Pendleton

    IPC: H01L29/00

    CPC classification number: H01L21/7624 ,  H01L21/3081 ,  H01L21/31612 ,  H01L21/76283

    Abstract: Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.

    Abstract translation: 公开了在绝缘体上硅（SOI）区域和体硅区域中形成或蚀刻硅沟槽隔离（STI）的方法以及如此形成的半导体器件。 可以通过使用STI掩模蚀刻到最上层的硅层，在SOI和体硅区域中同时蚀刻STI，进行蚀刻到体硅区域中期望的深度并停止在SOI区域的埋入绝缘体上的定时蚀刻 ，并蚀刻穿过SOI区域的埋层绝缘体。 用于该过程的掩埋绝缘体蚀刻可以以很少的复杂性作为硬掩模去除步骤的一部分来完成。 此外，通过为体区和SOI区域选择相同的深度，避免了后续CMP工艺的问题。 本发明还清除了可能存在氮化硅残留的SOI和体区之间的边界。

    Hard mask integrated etch process for patterning of silicon oxide and other dielectric materials
    9.
    发明授权
    Hard mask integrated etch process for patterning of silicon oxide and other dielectric materials 失效
    用于图案化氧化硅和其它介电材料的硬掩模集成蚀刻工艺

    公开(公告)号：US06869542B2

    公开(公告)日：2005-03-22

    申请号：US10249047

    申请日：2003-03-12

    Applicant: Sadanand V. Desphande ,  David Dobuzinsky ,  Arpan P. Mahorowala ,  Tina Wagner ,  Richard Wise

    Inventor： Sadanand V. Desphande ,  David Dobuzinsky ,  Arpan P. Mahorowala ,  Tina Wagner ,  Richard Wise

    IPC: B44C1/22 ,  H01L21/00 ,  H01L21/027 ,  H01L21/311

    CPC classification number: H01L21/31144 ,  H01L21/0276 ,  H01L21/31116

    Abstract: Form an opening in a dielectric layer formed on a substrate comprises depositing a hard mask composed of an etch resistant material over a dielectric layer, e.g. a silicon oxide. Use a photoresist mask to expose the hard mask. Use a fluorocarbon plasma to etch through the window to form an opening through the hard mask. Then etch through the hard mask opening to pattern the dielectric layer. The hard mask comprises an RCH/RCHX material with the structural formula R:C:H or R:C:H:X, where R is selected from Si, Ge, B, Sn, Fe, Ti and X is selected from O, N, S and F. The plasma etching process employs a) a gas mixture comprising N2; fluorocarbon (CHF3, C4F8, C4F6, CF4, CH2F2, CH3F); an oxidizer (O2, CO2), and a noble diluent (Ar, He); b) a high DC bias (500-3000 Volts bias on the wafer); 3) medium pressure (20-100 mT.; and d) moderate temperatures (−20 to 60°).

    Abstract translation: 在形成在基板上的电介质层中形成开口，包括在电介质层上沉积由耐蚀刻材料构成的硬掩模， 氧化硅。 使用光刻胶掩模露出硬掩模。 使用氟碳等离子体通过窗口蚀刻以形成通过硬掩模的开口。 然后蚀刻穿过硬掩模开口以对介电层进行图案化。 硬掩模包括具有结构式R：C：H或R：C：H：X的RCH / RCHX材料，其中R选自Si，Ge，B，Sn，Fe，Ti和X选自O， N，S和F.等离子体蚀刻工艺使用a）包含N 2的气体混合物; 碳氟化合物（CHF 3，C 4 F 8，C 4 F 6，CF 4，CH 2 F 2，CH 3 F）; 氧化剂（O 2，CO 2）和稀有稀释剂（Ar，He）; b）高直流偏置（晶片上的500-3000伏偏压）; 3）中压（20-100mT;和d）中等温度（-20至60°）。

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