A method and system for synthesizing digital clock signals for an electronic device under test having a plurality of pins, said method including generating centrally a reference clock, and distributing said reference clock to a number of electronic circuits, each of said electronic circuit having a test signal processor controlling electrically said pins of said device under test with predetermined signal pattern, characterized by synthesizing locally at said test signal processor a digital clock signal, said digital clock signal being individual for said pin of said device under test electrically controlled by said test signal processor.