A system to write to a plurality of memory cells coupled to a word line, each of the plurality of memory cells comprising a transistor having a source, a drain, a body and a gate coupled to the word line. Some embodiments provide biasing of one or more of the plurality of memory cells in saturation to inject charge carriers into the body of the one or more of the plurality of memory cells, and biasing of each of the plurality of memory cells in accumulation to tunnel charge carriers from the body of each of the plurality of memory cells to the gate of each of the plurality of memory cells.