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公开(公告)号:US07958336B2
公开(公告)日:2011-06-07
申请号:US12164666
申请日:2008-06-30
申请人: Sagi Lahav , Guy Patkin , Zeev Sperber , Herbert Hum , Shih-Lien Lu , Srikanth T. Srinivasan
发明人: Sagi Lahav , Guy Patkin , Zeev Sperber , Herbert Hum , Shih-Lien Lu , Srikanth T. Srinivasan
IPC分类号: G06F9/30
CPC分类号: G06F9/3838 , G06F9/3017 , G06F9/3834 , G06F9/384 , G06F9/3859
摘要: A device and method may fetch an instruction or micro-operation for execution. An indication may be made as to whether the instruction is dependent upon any source values corresponding to a set of previously fetched instructions. A value may be stored corresponding to each source value from which the first instruction depends. An indication may be made for each of the set of sources of the instruction, whether the source depends on a previously loaded value or source, where indicating may include storing a value corresponding to the indication. The instruction may be executed after the stored values associated with the instruction indicate the dependencies are satisfied.
摘要翻译: 设备和方法可以获取用于执行的指令或微操作。 可以指示该指令是否取决于对应于一组先前获取的指令的任何源值。 可以存储对应于第一指令所依赖的每个源值的值。 可以针对指令的每个源的指示,源是否依赖于先前加载的值或源,其中指示可以包括存储对应于指示的值。 可以在与指令相关联的存储值表示满足依赖性之后执行指令。
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公开(公告)号:US20060054977A1
公开(公告)日:2006-03-16
申请号:US10942019
申请日:2004-09-16
申请人: Dinesh Somasekhar , Shekhar Borkar , Vivek De , Yibin Ye , Muhammad Khellah , Fabrice Paillet , Stephen Tang , Ali Keshavarzi , Shih-Lien Lu
发明人: Dinesh Somasekhar , Shekhar Borkar , Vivek De , Yibin Ye , Muhammad Khellah , Fabrice Paillet , Stephen Tang , Ali Keshavarzi , Shih-Lien Lu
IPC分类号: H01L29/76
CPC分类号: H01L27/115 , G11C11/404 , G11C16/0416
摘要: A memory device is provided that includes a plurality of memory cells where each memory cell includes a source region, a drain region and a floating gate. A coupling bit-line is also provided that extends over at least one column of the plurality of memory cells. The coupling bit-line may be formed on each of the floating gates of memory cells forming the column of the plurality of memory cells. The coupling bit-line may also be formed within a well of each of memory cells forming the column of the plurality of memory cells.
摘要翻译: 提供一种存储器件,其包括多个存储器单元,其中每个存储器单元包括源极区域,漏极区域和浮动栅极。 还提供了在多个存储单元中的至少一列延伸的耦合位线。 耦合位线可以形成在形成多个存储单元的列的存储单元的每个浮置栅极上。 耦合位线也可以形成在形成多个存储器单元的列的每个存储单元的阱中。
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公开(公告)号:US20050145886A1
公开(公告)日:2005-07-07
申请号:US10750572
申请日:2003-12-31
申请人: Ali Keshavarzi , Stephen Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
发明人: Ali Keshavarzi , Stephen Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
IPC分类号: G11C11/404 , H01L21/8239 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/78
CPC分类号: G11C11/404 , G11C2211/4016 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L29/7841
摘要: Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.
摘要翻译: 一些实施例提供了包括体区,源区和漏区的存储单元。 主体区域掺杂有第一类型的电荷载流子,源极区域设置在体区中并掺杂有第二类型的电荷载流子,并且漏极区域设置在体区中并掺杂有第二类型的载流子 类型。 主体区域和源极区域形成第一结,主体区域和漏极区域形成第二结,并且在第一接合点不偏向的情况下,从体区域到源极区域的第一结的导电率基本上 在第二接头不偏差的情况下,小于从体区到漏区的第二结的导电性。
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公开(公告)号:US20050135169A1
公开(公告)日:2005-06-23
申请号:US10740551
申请日:2003-12-22
申请人: Dinesh Somasekhar , Yibin Ye , Muhammad Khellah , Fabrice Paillet , Stephen Tang , Ali Keshavarzi , Shih-Lien Lu , Vivek De
发明人: Dinesh Somasekhar , Yibin Ye , Muhammad Khellah , Fabrice Paillet , Stephen Tang , Ali Keshavarzi , Shih-Lien Lu , Vivek De
IPC分类号: G11C7/14 , G11C7/18 , G11C11/4097 , G11C11/4099 , G11C7/02
CPC分类号: G11C11/4099 , G11C7/14 , G11C7/18 , G11C11/4097
摘要: An apparatus and method for generating a reference in a memory circuit are disclosed. At least two dummy bit-cells are used to generate a reference voltage. One cell has high value stored and the other has a low value stored. The cells are activated and discharged into respective bit-lines. The bit-lines are equalized during the discharge process to generate a reference that is approximately a mid point between a high value cell and a low value cell.
摘要翻译: 公开了一种用于在存储器电路中产生参考的装置和方法。 使用至少两个伪位单元来产生参考电压。 一个单元格具有高存储值,另一个存储值较低。 电池被激活并放电到相应的位线。 在放电过程期间,位线被均衡以产生大约高值单元和低值单元之间的中点的参考。
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公开(公告)号:US20150085589A1
公开(公告)日:2015-03-26
申请号:US14037745
申请日:2013-09-26
申请人: Shih-Lien Lu , Ying-Chen Lin , Chia-Lin Yang
发明人: Shih-Lien Lu , Ying-Chen Lin , Chia-Lin Yang
CPC分类号: G11C7/08 , G11C7/065 , G11C7/1045
摘要: Apparatus, systems, and methods for data movement in a memory device are described. In one embodiment, a memory controller comprises logic to move a row of data from a first row of a memory in a first section of a memory device to a second row of memory in a second section of the memory device without passing the data through a communication interface. Other embodiments are also disclosed and claimed.
摘要翻译: 描述用于存储器件中的数据移动的装置,系统和方法。 在一个实施例中,存储器控制器包括将存储器设备的第一部分中的存储器的第一行的数据行移动到存储器设备的第二部分中的第二行存储器的逻辑,而不用通过数据通过 通讯接口 还公开并要求保护其他实施例。
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公开(公告)号:US20120297161A1
公开(公告)日:2012-11-22
申请号:US13550817
申请日:2012-07-17
申请人: David Champagne , Abhishek Tiwari , Wei Wu , Christopher J. Hughes , Sanjeev Kumar , Shih-Lien Lu
发明人: David Champagne , Abhishek Tiwari , Wei Wu , Christopher J. Hughes , Sanjeev Kumar , Shih-Lien Lu
IPC分类号: G06F12/10
CPC分类号: G06F12/1036 , G06F12/1009 , G06F12/1027 , G06F2212/681
摘要: In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed.
摘要翻译: 在一个实施例中,本发明包括翻译后备缓冲器(TLB),用于存储每个具有翻译部分以存储虚拟地址(VA)至物理地址(PA)转换)的条目,以及存储用于存储器的位的第二部分 与VA到PA转换相关联的页面,其中位指示存储器页面中的信息的属性。 描述和要求保护其他实施例。
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公开(公告)号:US20070164787A1
公开(公告)日:2007-07-19
申请号:US11234548
申请日:2005-09-23
IPC分类号: H03K19/173 , G06F7/38
CPC分类号: G01R31/31922 , G01R31/31726 , H03K5/1534 , H04L7/0083 , H04L7/033
摘要: Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.
摘要翻译: 两个锁存器在时钟信号的转变时存储数据信号的状态。 比较逻辑比较两个锁存器的输出,并产生一个信号以指示输出是相等还是不相等。 描述和要求保护使用锁存器和比较逻辑的系统。
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公开(公告)号:US20060054933A1
公开(公告)日:2006-03-16
申请号:US11268098
申请日:2005-11-07
申请人: Ali Keshavarzi , Stephen Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
发明人: Ali Keshavarzi , Stephen Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
IPC分类号: H01L27/10
CPC分类号: G11C11/404 , G11C2211/4016 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L29/7841
摘要: Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.
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公开(公告)号:US07002842B2
公开(公告)日:2006-02-21
申请号:US10721184
申请日:2003-11-26
申请人: Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien Lu , Vivek K. De
发明人: Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien Lu , Vivek K. De
IPC分类号: G11C11/34
CPC分类号: H01L27/108 , G11C11/404
摘要: Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell.
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公开(公告)号:US20060002211A1
公开(公告)日:2006-01-05
申请号:US10881001
申请日:2004-06-30
申请人: Yibin Ye , Dinesh Somasekhar , Muhammad Khellah , Fabrice Paillet , Stephen Tang , Ali Keshavarzi , Shih-Lien Lu , Vivek De
发明人: Yibin Ye , Dinesh Somasekhar , Muhammad Khellah , Fabrice Paillet , Stephen Tang , Ali Keshavarzi , Shih-Lien Lu , Vivek De
IPC分类号: G11C7/00
CPC分类号: G11C11/405
摘要: A two transistor memory cell includes a write transistor and a read transistor. When reading the memory cell, the read transistor is turned on, and a voltage develops on a read bit line.
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