发明申请
- 专利标题: FAULT-TOLERANT CLOCK GENERATOR
- 专利标题(中): 容错时钟发生器
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申请号: US11456332申请日: 2006-07-10
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公开(公告)号: US20060250160A1公开(公告)日: 2006-11-09
- 发明人: Kun-Yung Chang , Mark Horowitz
- 申请人: Kun-Yung Chang , Mark Horowitz
- 申请人地址: US CA Los Altos
- 专利权人: RAMBUS INC.
- 当前专利权人: RAMBUS INC.
- 当前专利权人地址: US CA Los Altos
- 主分类号: G01R13/00
- IPC分类号: G01R13/00 ; H03K19/00 ; G01R29/26 ; H01L25/00
摘要:
A fault-tolerant clock generation circuit. First and second clock signal generators are provided to generate first and second clock signals. The second clock signal generator includes a locked loop circuit that, in a first operating mode, adjusts the phase of the second clock signal as necessary to maintain phase alignment between the first and second clock signals. A fail detect circuit is provided to determine whether a failure relating to generation of the first clock signal has occurred and, if so, to assert a hold signal. The locked loop circuit responds to assertion of the hold signal by transitioning to a second operating mode in which the phase of the second clock signal is not adjusted.
公开/授权文献
- US07467320B2 Fault-tolerant clock generator 公开/授权日:2008-12-16