公开(公告)号：US12301227B2

公开(公告)日：2025-05-13

申请号：US18347376

申请日：2023-07-05

Applicant: Rambus Inc.

Inventor： Ian Shaeffer

IPC: H03K19/00 ,  G11C5/06 ,  G11C5/14 ,  G11C7/10 ,  G11C11/4063 ,  G11C11/413 ,  G11C16/06 ,  H03K19/0175

Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

公开(公告)号：US12301193B2

公开(公告)日：2025-05-13

申请号：US18236857

申请日：2023-08-22

Applicant: Rambus Inc.

Inventor： Cosmin Iorga ,  Ruibing Zhang

IPC: H03H11/04

Abstract: A pulse filter circuit is configured to eliminate pulses that are less than a specified duration and pass those that are greater than the specified duration. A buffer receives a signal and applies the buffered signal to a resistance-capacitance charging-discharging circuit (e.g., RC filter). When the output of the RC filter has, in response to the buffered signal, charged or discharged, as appropriate, to cause the output of a slicer to change, logic circuitry controls switching circuitry to pull the output of the RC filter to be fully charged or discharged, respectively. In this manner, pulses that are too short to charge/discharge the RC filter enough to cross the threshold of the slicer do not reach the slicer circuit output, but pulses that are long enough to cross the slicer threshold are transmitted by the slicer.

公开(公告)号：US12300345B2

公开(公告)日：2025-05-13

申请号：US18581694

申请日：2024-02-20

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C7/10

Abstract: A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure.

公开(公告)号：US12298926B2

公开(公告)日：2025-05-13

申请号：US18365696

申请日：2023-08-04

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Craig E. Hampel ,  Scott C. Best ,  John Yan

IPC: G06F13/16

Abstract: Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.

公开(公告)号：US12298848B2

公开(公告)日：2025-05-13

申请号：US18433897

申请日：2024-02-06

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Craig E. Hampel

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10 ,  G06F11/16 ,  H03M13/09

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.

公开(公告)号：US12298842B2

公开(公告)日：2025-05-13

申请号：US18586907

申请日：2024-02-26

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Catherine Chen ,  Scott C. Best ,  John Eric Linstadt ,  Frederick A. Ware

IPC: G06F11/07 ,  G06F13/00 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26 ,  G11C29/44

Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

公开(公告)号：US20250147875A1

公开(公告)日：2025-05-08

申请号：US18920086

申请日：2024-10-18

Applicant: Rambus Inc.

Inventor： Torsten Partsch

IPC: G06F12/02 ,  G11C29/42

Abstract: A memory device supports low power operation by facilitating staggered access to row segments within a row of a memory bank. Upon receiving an activate command to activate a row, the memory device sequentially activates a plurality of local wordlines associated with the row with a stagger interval between activations. Upon receiving an access command associated with the activated row, the memory device sequentially initiates column operations for respective row segments with the same stagger interval between the column operations. The memory device may furthermore facilitate error correction code operations in a staggered manner by sequentially performing computations associated with the different row segments.

公开(公告)号：US20250138750A1

公开(公告)日：2025-05-01

申请号：US18920418

申请日：2024-10-18

Applicant: Rambus Inc.

Inventor： Torsten Partsch

IPC: G06F3/06

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) dynamic random access memory (DRAM) device is disclosed. The IC DRAM device includes memory core circuitry organized into bank groups of storage cells, each bank group accessible via a corresponding bank group address. A command/address (C/A) interface receives C/A information defining a joint command. The joint command includes information specifying a first memory access operation, a first bank group address associated with the first memory access operation, and a second memory access operation to be automatically directed to the first bank group address.

公开(公告)号：US20250138732A1

公开(公告)日：2025-05-01

申请号：US18922774

申请日：2024-10-22

Applicant: Rambus Inc.

Inventor： J. James Tringali

IPC: G06F3/06

Abstract: Technologies for hardware-based memory access telemetry tracking are described. A receiver circuit includes analog and digital circuitry. A memory controller includes a processing pipeline with a first processing stage to update and record a first number of access counts targeting a logical grouping of memory locations and a second processing stage to continuously sort the first number of access counts and their associated address tags corresponding to the logical grouping of memory locations, keeping only the access counts with unique address tags.

公开(公告)号：US20250130739A1

公开(公告)日：2025-04-24

申请号：US18935798

申请日：2024-11-04

Applicant: Rambus Inc.

Inventor： Lei Luo ,  John C. Eble, III

IPC: G06F3/06

Abstract: Technologies for converting quad data rates on a host interface to double data rates on a memory interface are described. One memory module includes a data buffer device with a host-side interface circuit that sends or receives first data to and from a host device at a quad data rate and a memory-side interface circuit that sends or receives second data to and from a set of memory devices at a first specified data rate that is less than the quad data rate. The memory module includes conversion circuitry to down-convert the first data at the quad data rate to the second data at the first specified data rate and up-convert the second data at the first specified data rate to the first data at the quad data rate.