- 专利标题： Bitline exclusion in verification operation
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申请号： US11153188申请日： 2005-06-15
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公开(公告)号： US20060285390A1公开(公告)日： 2006-12-21
- 发明人: Hendrik Hartono , Aaron Yip , Benjamin Louie
- 申请人： Hendrik Hartono , Aaron Yip , Benjamin Louie
- 专利权人： Micron Technology, Inc.
- 当前专利权人： Micron Technology, Inc.
- 主分类号： G11C11/34
- IPC分类号： G11C11/34
摘要：
Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.
公开/授权文献
- US07274607B2 Bitline exclusion in verification operation 公开/授权日：2007-09-25
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