公开(公告)号：US07274607B2

公开(公告)日：2007-09-25

申请号：US11153188

申请日：2005-06-15

申请人： Hendrik Hartono ,  Aaron Yip ,  Benjamin Louie

发明人： Hendrik Hartono ,  Aaron Yip ,  Benjamin Louie

IPC分类号： G11C7/12

CPC分类号： G11C16/3454 ,  G11C29/83 ,  G11C29/832

摘要： Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.

摘要翻译： 用于禁止用于验证操作的错误位线以及用于确定编程操作是否失败的方法和装置包括为坏位线设置位线禁止锁存器，以及如果排除了位线，则禁止程序锁存器的操作，或者如果编程操作 失败了

公开(公告)号：US20060285390A1

公开(公告)日：2006-12-21

申请号：US11153188

申请日：2005-06-15

申请人： Hendrik Hartono ,  Aaron Yip ,  Benjamin Louie

发明人： Hendrik Hartono ,  Aaron Yip ,  Benjamin Louie

IPC分类号： G11C11/34

CPC分类号： G11C16/3454 ,  G11C29/83 ,  G11C29/832

摘要： Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.

公开(公告)号：US07486530B2

公开(公告)日：2009-02-03

申请号：US11116842

申请日：2005-04-28

申请人： Hendrik Hartono ,  Benjamin Louie ,  Aaron Yip ,  Hagop A. Nazarian

发明人： Hendrik Hartono ,  Benjamin Louie ,  Aaron Yip ,  Hagop A. Nazarian

IPC分类号： G11C15/00 ,  G11C7/06 ,  G11C16/04

CPC分类号： G11C7/22 ,  G06F12/0893 ,  G11C16/3436 ,  G11C2207/2245 ,  G11C2216/14

摘要： A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer or data cache of a memory and the sense amplifiers, that allow for simple and rapid comparison of data bits and results in a signal flag indicating a data match or a mis-match. This allows for a simple parallel data bit comparison capability that allows a fast initial comparison result without requiring a time-consuming individual bit-by-bit data comparison. In one embodiment, two data blocks to be compared are divided into a number of paired segments, wherein each pair of segments are compared in parallel by a data comparison circuit, such that a mis-match can be located to the affected data segments or the results logically combined to indicate a match or mis-match for the complete data blocks.

摘要翻译： 描述了一种非易失性存储器件和数据比较电路，其有助于比较诸如存储器的I / O缓冲器或数据高速缓冲存储器和读出放大器的两个数据块之间的数据，其允许简单和快速地比较 数据位并产生指示数据匹配或不匹配的信号标志。 这允许一个简单的并行数据位比较功能，允许快速的初始比较结果，而不需要耗时的单独的逐位数据比较。 在一个实施例中，要比较的两个数据块被分成多个成对段，其中每对段被数据比较电路并行地比较，使得可以将错误匹配定位到受影响的数据段或 结果逻辑组合以指示完整数据块的匹配或不匹配。

公开(公告)号：US20070285988A1

公开(公告)日：2007-12-13

申请号：US11842531

申请日：2007-08-21

申请人： Hendrik Hartono ,  Aaron Yip ,  Benjamin Louie

发明人： Hendrik Hartono ,  Aaron Yip ,  Benjamin Louie

IPC分类号： G11C7/12 ,  G11C7/06

CPC分类号： G11C16/3454 ,  G11C29/83 ,  G11C29/832

摘要： Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.

摘要翻译： 用于禁止用于验证操作的错误位线以及用于确定编程操作是否失败的方法和装置包括为坏位线设置位线禁止锁存器，以及如果排除了位线，则禁止程序锁存器的操作，或者如果编程操作 失败了

公开(公告)号：US07254049B2

公开(公告)日：2007-08-07

申请号：US11580660

申请日：2006-10-13

申请人： Hendrik Hartono ,  Benjamin Louie ,  Aaron Yip ,  Hagop A. Nazarian

发明人： Hendrik Hartono ,  Benjamin Louie ,  Aaron Yip ,  Hagop A. Nazarian

IPC分类号： G11C15/00 ,  G11C7/10

CPC分类号： G11C7/22 ,  G06F12/0893 ,  G11C16/3436 ,  G11C2207/2245 ,  G11C2216/14

摘要： A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer or data cache of a memory and the sense amplifiers, that allow for simple and rapid comparison of data bits and results in a signal flag indicating a data match or a mis-match. This allows for a simple parallel data bit comparison capability that allows a fast initial comparison result without requiring a time-consuming individual bit-by-bit data comparison. In one embodiment, two data blocks to be compared are divided into a number of paired segments, wherein each pair of segments are compared in parallel by a data comparison circuit, such that a mis-match can be located to the affected data segments or the results logically combined to indicate a match or mis-match for the complete data blocks.

公开(公告)号：US20060245272A1

公开(公告)日：2006-11-02

申请号：US11116842

申请日：2005-04-28

申请人： Hendrik Hartono ,  Benjamin Louie ,  Aaron Yip ,  Hagop Nazarian

发明人： Hendrik Hartono ,  Benjamin Louie ,  Aaron Yip ,  Hagop Nazarian

IPC分类号： G11C7/06

CPC分类号： G11C7/22 ,  G06F12/0893 ,  G11C16/3436 ,  G11C2207/2245 ,  G11C2216/14

摘要： A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer or data cache of a memory and the sense amplifiers, that allow for simple and rapid comparison of data bits and results in a signal flag indicating a data match or a mis-match. This allows for a simple parallel data bit comparison capability that allows a fast initial comparison result without requiring a time-consuming individual bit-by-bit data comparison. In one embodiment, two data blocks to be compared are divided into a number of paired segments, wherein each pair of segments are compared in parallel by a data comparison circuit, such that a mis-match can be located to the affected data segments or the results logically combined to indicate a match or mis-match for the complete data blocks.

公开(公告)号：US07532524B2

公开(公告)日：2009-05-12

申请号：US11842531

申请日：2007-08-21

申请人： Hendrik Hartono ,  Aaron Yip ,  Benjamin Louie

发明人： Hendrik Hartono ,  Aaron Yip ,  Benjamin Louie

IPC分类号： G11C7/00

CPC分类号： G11C16/3454 ,  G11C29/83 ,  G11C29/832

摘要： Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.

摘要翻译： 用于禁止用于验证操作的错误位线以及用于确定编程操作是否失败的方法和装置包括为坏位线设置位线禁止锁存器，以及如果排除了位线，则禁止程序锁存器的操作，或者如果编程操作 失败了

公开(公告)号：US20070030739A1

公开(公告)日：2007-02-08

申请号：US11580660

申请日：2006-10-13

申请人： Hendrik Hartono ,  Benjamin Louie ,  Aaron Yip ,  Hagop Nazarian

发明人： Hendrik Hartono ,  Benjamin Louie ,  Aaron Yip ,  Hagop Nazarian

IPC分类号： G11C7/06

CPC分类号： G11C7/22 ,  G06F12/0893 ,  G11C16/3436 ,  G11C2207/2245 ,  G11C2216/14

摘要： A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer or data cache of a memory and the sense amplifiers, that allow for simple and rapid comparison of data bits and results in a signal flag indicating a data match or a mis-match. This allows for a simple parallel data bit comparison capability that allows a fast initial comparison result without requiring a time-consuming individual bit-by-bit data comparison. In one embodiment, two data blocks to be compared are divided into a number of paired segments, wherein each pair of segments are compared in parallel by a data comparison circuit, such that a mis-match can be located to the affected data segments or the results logically combined to indicate a match or mis-match for the complete data blocks.

摘要翻译： 描述了一种非易失性存储器件和数据比较电路，其有助于比较诸如存储器的I / O缓冲器或数据高速缓冲存储器和读出放大器的两个数据块之间的数据，其允许简单和快速地比较 数据位并产生指示数据匹配或不匹配的信号标志。 这允许一个简单的并行数据位比较功能，允许快速的初始比较结果，而不需要耗时的单独的逐位数据比较。 在一个实施例中，要比较的两个数据块被分成多个成对段，其中每对段被数据比较电路并行地比较，使得可以将错误匹配定位到受影响的数据段或 结果逻辑组合以指示完整数据块的匹配或不匹配。

公开(公告)号：US20100052771A1

公开(公告)日：2010-03-04

申请号：US12202064

申请日：2008-08-29

申请人： Hendrik Hartono

发明人： Hendrik Hartono

IPC分类号： G05F1/10 ,  H03L7/06

CPC分类号： H03L7/00 ,  H02M3/073 ,  H02M2003/077

摘要： A system for driving multiple charge pumps in a single unit is disclosed. The charge pump system includes a set of multiple charge pumps arranged in parallel. The charge pumps are connected to a clock signal generator, which generates clock signals that direct the charging of the charge pumps and are offset in time from one another. The clock signals may be generated such that rising edges of the clock signals are separated by a specified time interval. The clock signals may be generated by a ring oscillator using signals provided by stages of the oscillator to generate the multiple signals. The clock signals may also be generated by providing a single input clock signal to a multi-phase generator, which outputs a set of clock signals having different phases based on the input clock signal. The system may also be configured to generate the offset clock signals using other methods, such as using a programmed microcontroller or using spread spectrum techniques.

摘要翻译： 公开了一种用于在单个单元中驱动多个电荷泵的系统。 电荷泵系统包括并联布置的一组多个电荷泵。 电荷泵连接到时钟信号发生器，其产生引导电荷泵的充电的时钟信号并且在时间上彼此抵消。 可以产生时钟信号，使得时钟信号的上升沿被隔开指定的时间间隔。 时钟信号可以由环形振荡器使用由振荡器的级提供的信号来产生以产生多个信号。 还可以通过向多相发生器提供单个输入时钟信号来产生时钟信号，多相发生器基于输入时钟信号输出具有不同相位的一组时钟信号。 该系统还可以被配置为使用其他方法（例如使用编程的微控制器或使用扩频技术）生成偏移时钟信号。