公开(公告)号：US20060285390A1

公开(公告)日：2006-12-21

申请号：US11153188

申请日：2005-06-15

申请人： Hendrik Hartono ,  Aaron Yip ,  Benjamin Louie

发明人： Hendrik Hartono ,  Aaron Yip ,  Benjamin Louie

IPC分类号： G11C11/34

CPC分类号： G11C16/3454 ,  G11C29/83 ,  G11C29/832

摘要： Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.

公开(公告)号：US07486530B2

公开(公告)日：2009-02-03

申请号：US11116842

申请日：2005-04-28

申请人： Hendrik Hartono ,  Benjamin Louie ,  Aaron Yip ,  Hagop A. Nazarian

发明人： Hendrik Hartono ,  Benjamin Louie ,  Aaron Yip ,  Hagop A. Nazarian

IPC分类号： G11C15/00 ,  G11C7/06 ,  G11C16/04

CPC分类号： G11C7/22 ,  G06F12/0893 ,  G11C16/3436 ,  G11C2207/2245 ,  G11C2216/14

摘要： A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer or data cache of a memory and the sense amplifiers, that allow for simple and rapid comparison of data bits and results in a signal flag indicating a data match or a mis-match. This allows for a simple parallel data bit comparison capability that allows a fast initial comparison result without requiring a time-consuming individual bit-by-bit data comparison. In one embodiment, two data blocks to be compared are divided into a number of paired segments, wherein each pair of segments are compared in parallel by a data comparison circuit, such that a mis-match can be located to the affected data segments or the results logically combined to indicate a match or mis-match for the complete data blocks.

摘要翻译： 描述了一种非易失性存储器件和数据比较电路，其有助于比较诸如存储器的I / O缓冲器或数据高速缓冲存储器和读出放大器的两个数据块之间的数据，其允许简单和快速地比较 数据位并产生指示数据匹配或不匹配的信号标志。 这允许一个简单的并行数据位比较功能，允许快速的初始比较结果，而不需要耗时的单独的逐位数据比较。 在一个实施例中，要比较的两个数据块被分成多个成对段，其中每对段被数据比较电路并行地比较，使得可以将错误匹配定位到受影响的数据段或 结果逻辑组合以指示完整数据块的匹配或不匹配。

公开(公告)号：US20070285988A1

公开(公告)日：2007-12-13

申请号：US11842531

申请日：2007-08-21

申请人： Hendrik Hartono ,  Aaron Yip ,  Benjamin Louie

发明人： Hendrik Hartono ,  Aaron Yip ,  Benjamin Louie

IPC分类号： G11C7/12 ,  G11C7/06

CPC分类号： G11C16/3454 ,  G11C29/83 ,  G11C29/832

摘要： Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.

摘要翻译： 用于禁止用于验证操作的错误位线以及用于确定编程操作是否失败的方法和装置包括为坏位线设置位线禁止锁存器，以及如果排除了位线，则禁止程序锁存器的操作，或者如果编程操作 失败了

公开(公告)号：US07254049B2

公开(公告)日：2007-08-07

申请号：US11580660

申请日：2006-10-13

申请人： Hendrik Hartono ,  Benjamin Louie ,  Aaron Yip ,  Hagop A. Nazarian

发明人： Hendrik Hartono ,  Benjamin Louie ,  Aaron Yip ,  Hagop A. Nazarian

IPC分类号： G11C15/00 ,  G11C7/10

CPC分类号： G11C7/22 ,  G06F12/0893 ,  G11C16/3436 ,  G11C2207/2245 ,  G11C2216/14

摘要： A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer or data cache of a memory and the sense amplifiers, that allow for simple and rapid comparison of data bits and results in a signal flag indicating a data match or a mis-match. This allows for a simple parallel data bit comparison capability that allows a fast initial comparison result without requiring a time-consuming individual bit-by-bit data comparison. In one embodiment, two data blocks to be compared are divided into a number of paired segments, wherein each pair of segments are compared in parallel by a data comparison circuit, such that a mis-match can be located to the affected data segments or the results logically combined to indicate a match or mis-match for the complete data blocks.

公开(公告)号：US20060245272A1

公开(公告)日：2006-11-02

申请号：US11116842

申请日：2005-04-28

申请人： Hendrik Hartono ,  Benjamin Louie ,  Aaron Yip ,  Hagop Nazarian

发明人： Hendrik Hartono ,  Benjamin Louie ,  Aaron Yip ,  Hagop Nazarian

IPC分类号： G11C7/06

CPC分类号： G11C7/22 ,  G06F12/0893 ,  G11C16/3436 ,  G11C2207/2245 ,  G11C2216/14

摘要： A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer or data cache of a memory and the sense amplifiers, that allow for simple and rapid comparison of data bits and results in a signal flag indicating a data match or a mis-match. This allows for a simple parallel data bit comparison capability that allows a fast initial comparison result without requiring a time-consuming individual bit-by-bit data comparison. In one embodiment, two data blocks to be compared are divided into a number of paired segments, wherein each pair of segments are compared in parallel by a data comparison circuit, such that a mis-match can be located to the affected data segments or the results logically combined to indicate a match or mis-match for the complete data blocks.

公开(公告)号：US07274607B2

公开(公告)日：2007-09-25

申请号：US11153188

申请日：2005-06-15

申请人： Hendrik Hartono ,  Aaron Yip ,  Benjamin Louie

发明人： Hendrik Hartono ,  Aaron Yip ,  Benjamin Louie

IPC分类号： G11C7/12

CPC分类号： G11C16/3454 ,  G11C29/83 ,  G11C29/832

摘要： Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.

摘要翻译： 用于禁止用于验证操作的错误位线以及用于确定编程操作是否失败的方法和装置包括为坏位线设置位线禁止锁存器，以及如果排除了位线，则禁止程序锁存器的操作，或者如果编程操作 失败了

公开(公告)号：US07532524B2

公开(公告)日：2009-05-12

申请号：US11842531

申请日：2007-08-21

申请人： Hendrik Hartono ,  Aaron Yip ,  Benjamin Louie

发明人： Hendrik Hartono ,  Aaron Yip ,  Benjamin Louie

IPC分类号： G11C7/00

CPC分类号： G11C16/3454 ,  G11C29/83 ,  G11C29/832

摘要： Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.

摘要翻译： 用于禁止用于验证操作的错误位线以及用于确定编程操作是否失败的方法和装置包括为坏位线设置位线禁止锁存器，以及如果排除了位线，则禁止程序锁存器的操作，或者如果编程操作 失败了

公开(公告)号：US20070030739A1

公开(公告)日：2007-02-08

申请号：US11580660

申请日：2006-10-13

申请人： Hendrik Hartono ,  Benjamin Louie ,  Aaron Yip ,  Hagop Nazarian

发明人： Hendrik Hartono ,  Benjamin Louie ,  Aaron Yip ,  Hagop Nazarian

IPC分类号： G11C7/06

CPC分类号： G11C7/22 ,  G06F12/0893 ,  G11C16/3436 ,  G11C2207/2245 ,  G11C2216/14

摘要： A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer or data cache of a memory and the sense amplifiers, that allow for simple and rapid comparison of data bits and results in a signal flag indicating a data match or a mis-match. This allows for a simple parallel data bit comparison capability that allows a fast initial comparison result without requiring a time-consuming individual bit-by-bit data comparison. In one embodiment, two data blocks to be compared are divided into a number of paired segments, wherein each pair of segments are compared in parallel by a data comparison circuit, such that a mis-match can be located to the affected data segments or the results logically combined to indicate a match or mis-match for the complete data blocks.

摘要翻译： 描述了一种非易失性存储器件和数据比较电路，其有助于比较诸如存储器的I / O缓冲器或数据高速缓冲存储器和读出放大器的两个数据块之间的数据，其允许简单和快速地比较 数据位并产生指示数据匹配或不匹配的信号标志。 这允许一个简单的并行数据位比较功能，允许快速的初始比较结果，而不需要耗时的单独的逐位数据比较。 在一个实施例中，要比较的两个数据块被分成多个成对段，其中每对段被数据比较电路并行地比较，使得可以将错误匹配定位到受影响的数据段或 结果逻辑组合以指示完整数据块的匹配或不匹配。

公开(公告)号：US20100142280A1

公开(公告)日：2010-06-10

申请号：US12703901

申请日：2010-02-11

申请人： Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

发明人： Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

IPC分类号： G11C16/04

CPC分类号： G11C16/10

摘要： A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

摘要翻译： 通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为 目标存储单元未编程。 在制造存储器件之后，可以选择初始编程电压和阶跃电压。

公开(公告)号：US20080074933A1

公开(公告)日：2008-03-27

申请号：US11515629

申请日：2006-09-05

申请人： Benjamin Louie ,  Yunqiu Wan ,  Aaron Yip ,  Jin-Man Han

发明人： Benjamin Louie ,  Yunqiu Wan ,  Aaron Yip ,  Jin-Man Han

IPC分类号： G11C7/10

CPC分类号： G11C7/1042 ,  G11C7/1051 ,  G11C16/26 ,  G11C2207/2245

摘要： A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is user selected. This random cache read mode allows for a memory with a random page read capability, in which the address of the next page of data to be read is user selectable, which benefits from the low latency of a cache read mode of operation due to concurrent data sensing and data I/O.

摘要翻译： 描述了利用高速缓存读取操作模式的非易失性存储器，其中由读出放大器从存储器阵列读取/感测存储器的下一页，同时从存储器I / O缓冲器，其中下一页是用户选择的。 这种随机高速缓存读取模式允许具有随机页面读取功能的存储器，其中要读取的下一页数据的地址是用户可选择的，这受益于由于并发数据而导致的高速缓存读取操作模式的低等待时间 感测和数据I / O。