公开(公告)号：US09070459B2

公开(公告)日：2015-06-30

申请号：US13599757

申请日：2012-08-30

申请人： Xiaojun Yu ,  Jin-man Han ,  Aaron Yip

发明人： Xiaojun Yu ,  Jin-man Han ,  Aaron Yip

IPC分类号： G11C16/16 ,  G11C16/14 ,  G11C16/10 ,  G11C16/32 ,  G11C16/08 ,  G11C16/06 ,  G11C16/04

CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/14

摘要： Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.

摘要翻译： 装置，系统和方法可以操作以在耦合到位于基板上的可擦除存储器阵列的控制电路处接收外部擦除命令。 之后可以使全局选择栅极电压施加到耦合到可擦除存储器阵列的字线晶体管，在施加到衬底的电压已经达到约零伏特和最终擦除电压之间的预先选择的初始电压电平之后。

公开(公告)号：US08929120B2

公开(公告)日：2015-01-06

申请号：US13597917

申请日：2012-08-29

申请人： Aaron Yip

发明人： Aaron Yip

IPC分类号： G11C5/06

CPC分类号： G11C5/06 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/72

摘要： Memory devices, memory arrays, and methods of operation of memory arrays with segmentation. Segmentation elements can scale with the memory cells, and may be uni-directional or bi-directional diodes. Biasing lines in the array allow biasing of selected and unselected select devices and segmentation elements with any desired bias, and may use biasing devices of the same construction as the segmentation elements.

摘要翻译： 存储器件，存储器阵列以及具有分段的存储器阵列的操作方法。 分割元件可以与存储器单元成比例，并且可以是单向或双向二极管。 阵列中的偏置线允许以任何所希望的偏置来偏移选定和未选择的选择装置和分割元件，并且可以使用与分割元件相同结构的偏置装置。

公开(公告)号：US08259508B2

公开(公告)日：2012-09-04

申请号：US12847744

申请日：2010-07-30

申请人： Xiaojun Yu ,  Jin-man Han ,  Aaron Yip

发明人： Xiaojun Yu ,  Jin-man Han ,  Aaron Yip

IPC分类号： G11C16/16 ,  G11C16/14 ,  G11C16/10 ,  G11C16/32 ,  G11C16/08 ,  G11C16/06

CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/14

摘要： Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.

摘要翻译： 装置，系统和方法可以操作以在耦合到位于基板上的可擦除存储器阵列的控制电路处接收外部擦除命令。 之后可以使全局选择栅极电压施加到耦合到可擦除存储器阵列的字线晶体管，在施加到衬底的电压已经达到约零伏特和最终擦除电压之间的预先选择的初始电压电平之后。

公开(公告)号：US08184481B2

公开(公告)日：2012-05-22

申请号：US13084108

申请日：2011-04-11

申请人： Aaron Yip

发明人： Aaron Yip

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445

摘要： Memory devices and methods of their operation, where following an erasure of a string of memory cells, a selective compaction verify operation is performed on one or more, but less than all, of the memory cells of the string, and, if the selective compaction verify operation indicates compaction is desired, a soft programming pulse is applied to one or more of the memory cells of the string.

摘要翻译： 存储器件及其操作方法，其中在擦除一串存储器单元的情况下，在串的存储单元的一个或多个但少于全部执行选择性压实验证操作，并且如果选择性压缩 验证操作指示需要压缩，则将软编程脉冲施加到串的一个或多个存储单元。

公开(公告)号：US08174889B2

公开(公告)日：2012-05-08

申请号：US12703901

申请日：2010-02-11

申请人： Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

发明人： Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

IPC分类号： G11C16/04

CPC分类号： G11C16/10

摘要： A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

摘要翻译： 通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为 目标存储单元未编程。 在制造存储器件之后，可以选择初始编程电压和阶跃电压。

公开(公告)号：US20120069659A1

公开(公告)日：2012-03-22

申请号：US13308405

申请日：2011-11-30

申请人： Jin-Man Han ,  Aaron Yip

发明人： Jin-Man Han ,  Aaron Yip

IPC分类号： G11C16/06 ,  G11C16/26

CPC分类号： G11C29/846 ,  G11C29/82 ,  G11C2216/30

摘要： Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality of groups of regular columns and a plurality of groups of redundant columns. The apparatus also includes a plurality of data latches. Each of the data latches is configured to store data read from a respective one group of regular columns. The apparatus further includes a plurality of redundant data latches. Each of the redundant data latches is configured to store data read from a respective one group of redundant columns. The apparatus also includes a multiplexer configured to selectively output data from the plurality of data latches and the plurality of redundant data latches.

摘要翻译： 公开了装置和方法，例如涉及闪存装置的装置和方法。 一种这样的装置包括包括多个列的存储块。 每个列包括位线和位线上的多个存储单元。 多个列包括多组常规列和多组冗余列。 该装置还包括多个数据锁存器。 每个数据锁存器被配置为存储从相应的一组常规列读取的数据。 该装置还包括多个冗余数据锁存器。 每个冗余数据锁存器被配置为存储从相应的一组冗余列读取的数据。 该装置还包括多路复用器，其被配置为选择性地从多个数据锁存器和多个冗余数据锁存器输出数据。

公开(公告)号：US08064252B2

公开(公告)日：2011-11-22

申请号：US12276085

申请日：2008-11-21

申请人： Aaron Yip

发明人： Aaron Yip

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： A method for programming a memory device, a memory device, and a memory system are provided. According to at least one such method, a first programming pass generates a plurality of first programming pulses to increase the threshold voltages of target memory cells to either a pre-program level or to the highest programmed threshold. A second programming pass applies a plurality of second programming pulses to the target memory cells to increase their threshold voltages only if they were programmed to the pre-program level. The target memory cells programmed to their respective target threshold levels during the first pass are not programmed further.

摘要翻译： 提供了一种用于对存储器件，存储器件和存储器系统进行编程的方法。 根据至少一种这样的方法，第一编程通道产生多个第一编程脉冲，以将目标存储器单元的阈值电压增加到预编程级或最高编程阈值。 第二编程通道将多个第二编程脉冲施加到目标存储器单元，以便仅当它们被编程为预编程级时才增加它们的阈值电压。 在第一次通过期间被编程到它们各自的目标阈值水平的目标存储器单元没有进一步编程。

公开(公告)号：US20110249503A1

公开(公告)日：2011-10-13

申请号：US12756366

申请日：2010-04-08

申请人： Shigekazu Yamada ,  Aaron Yip

发明人： Shigekazu Yamada ,  Aaron Yip

IPC分类号： G11C16/04 ,  G11C16/02

CPC分类号： G11C16/102 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427

摘要： Methods for programming select gates, memory devices, and memory systems are disclosed. In one such method for programming, a program inhibit voltage is transferred from a source line to unselected bit lines. Bit line-to-bit line capacitance, between the unselected bit lines and selected bit lines to be program inhibited, boosts the bit line voltage of the selected, inhibited bit lines to a target inhibit voltage. In one embodiment, the voltage on the selected, inhibited bit line can be increased in a plurality of inhibit steps whereby either one, two, or all of the steps can be used during the programming of unprogrammed select gates.

摘要翻译： 公开了用于编程选择门，存储器件和存储器系统的方法。 在一种用于编程的方法中，程序禁止电压从源极线传送到未选位线。 在未被选择的位线和要被编程禁止的选定位线之间的位线对位线电容将所选择的禁止位线的位线电压升高到目标抑制电压。 在一个实施例中，可以在多个禁止步骤中增加所选择的禁止位线上的电压，由此在编程的未选择栅极的编程期间可以使用一个，两个或所有步骤。

公开(公告)号：US20110158003A1

公开(公告)日：2011-06-30

申请号：US13040855

申请日：2011-03-04

申请人： Aaron Yip

发明人： Aaron Yip

IPC分类号： G11C16/16

CPC分类号： G11C16/0483 ,  H01L27/115

摘要： An embodiment of a method of erasing a target memory cell includes grounding a selected word line commonly coupled to portions of a row of memory cells respectively formed on first well regions of a plurality of first well regions of a first conductivity type formed in a second well region of a second conductivity type, the at least one target memory cell coupled to the selected word line and formed on one of the first well regions, the first well regions electrically isolated from each other; applying a first voltage to the first well region on which the at least one target memory cell is formed; and applying a second voltage to unselected word lines, each unselected word line commonly coupled to portions of a row of memory cells not targeted for erasing and respectively formed on the first well regions.

摘要翻译： 擦除目标存储器单元的方法的一个实施例包括将所选择的字线接地，该选择的字线共同耦合到分别形成在形成于第二阱中的第一导电类型的多个第一阱区的第一阱区上的存储单元行的一部分 第二导电类型的区域，所述至少一个目标存储器单元耦合到所选择的字线并形成在所述第一阱区中的一个上，所述第一阱区彼此电隔离; 向形成有所述至少一个目标存储单元的所述第一阱区施加第一电压; 以及向未选择的字线施加第二电压，每个未选择的字线共同耦合到一行存储器单元的未被擦除并分别形成在第一阱区上的部分。

公开(公告)号：US07773412B2

公开(公告)日：2010-08-10

申请号：US11437706

申请日：2006-05-22

申请人： Hagop A. Nazarian ,  Aaron Yip

发明人： Hagop A. Nazarian ,  Aaron Yip

IPC分类号： G11C16/04

CPC分类号： G11C8/12 ,  G11C5/063 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521

摘要： A flash memory architecture that provides a mechanism for reducing floating gate to floating gate coupling. The floating gates of the memory cells are shifted, either vertically or horizontally thereby offsetting the floating gates of the memory cells to an intervening space between the gates of adjacent memory cells. The shift of the floating gates decreases the floating gate to floating gate coupling.

摘要翻译： 一种闪存架构，提供了将浮动栅极减少到浮动栅极耦合的机制。 存储器单元的浮动栅极被垂直或水平移位，从而将存储器单元的浮动栅极抵消到相邻存储器单元的栅极之间的中间空间。 浮动栅极的移位将浮动栅极减小到浮动栅极耦合。