Invention Application
- Patent Title: SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
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Application No.: US11425072Application Date: 2006-06-19
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Publication No.: US20060289904A1Publication Date: 2006-12-28
- Inventor: Mikio Tsujiuchi , Toshiaki Iwamatsu , Takashi Ipposhi
- Applicant: Mikio Tsujiuchi , Toshiaki Iwamatsu , Takashi Ipposhi
- Applicant Address: JP Chiyoda-ku
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Chiyoda-ku
- Priority: JP2005-184295 20050624
- Main IPC: H01L29/76
- IPC: H01L29/76

Abstract:
In the semiconductor device which has partial trench isolation as isolation between elements formed in an SOI substrate, resistance reduction of the source drain of a transistor and reduction of leakage current are aimed at. A MOS transistor is formed in the active region specified by the isolation insulating layer in the SOI layer formed on the buried oxide film layer (BOX layer). An isolation insulating layer is a partial trench isolation which has not reached a BOX layer, and source and drain regions include the first and the second impurity ion which differs in a mass number mutually.
Information query
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