发明申请
- 专利标题: Method and apparatus for enhanced CMP planarization using surrounded dummy design
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申请号: US11181433申请日: 2005-07-14
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公开(公告)号: US20070015365A1公开(公告)日: 2007-01-18
- 发明人: Hsien-Wei Chen , Hao-Yi Tsai , Hsueh-Chung Chen , Shin-Puu Jeng , Jian-Hong Lin , Chih-Tao Lin , Shih-Hsun Hsu
- 申请人: Hsien-Wei Chen , Hao-Yi Tsai , Hsueh-Chung Chen , Shin-Puu Jeng , Jian-Hong Lin , Chih-Tao Lin , Shih-Hsun Hsu
- 专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 主分类号: H01L21/461
- IPC分类号: H01L21/461
摘要:
In one embodiment, the disclosure relates to a method and apparatus for inserting dummy patterns in sparsely populated portions of a metal layer. The dummy pattern counters the effects of variations of pattern density in a semiconductor layout which can cause uneven post-polish film thickness. An algorithm according to one embodiment of the disclosure determines the size and location of the dummy patterns based on the patterns in the metal layer by first surrounding the metal structure with small dummy pattern and then filling any remaining voids with large dummy patterns.
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