A flash memory device is disclosed that comprises memory cells, a sense node connected to a selected bit line, a sense circuit configured to selectively provide a first voltage to a common node in accordance with a voltage level of the sense node, a first register connected to the sense node and the common node and configured to store data in accordance with a voltage level of the common node,a second register configured to store data in accordance with the voltage level of the sense node, a switch configured to provide a second voltage to the second register, and a discharge circuit configured to selectively discharge the sense node in accordance with the data stored in the second register.