公开(公告)号：US07566927B2

公开(公告)日：2009-07-28

申请号：US10840580

申请日：2004-05-07

申请人： Moo-Sung Kim ,  Yeong-Taek Lee ,  Seung-Jae Lee

发明人： Moo-Sung Kim ,  Yeong-Taek Lee ,  Seung-Jae Lee

IPC分类号： H01L29/788

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  H01L27/115

摘要： A flash memory device may include a memory cell array having a plurality of word lines, bit lines, and memory cells. Each memory cell may be arranged at an intersection of a corresponding word line and a corresponding bit line. The device may include a bit line voltage setting circuit for setting a voltage on a bit line of a given memory cell to be programmed to a variable bit line voltage or to a ground voltage. A variable bit line voltage generating circuit may be provided in the flash memory device for generating the variable bit line voltage. To facilitating programming of the device, a bit line voltage of a given memory cell to be programmed may be set based on a supply voltage of the device, so as to maintain a voltage difference based on the set bit line voltage above a given threshold voltage.

摘要翻译： 闪存器件可以包括具有多个字线，位线和存储器单元的存储单元阵列。 每个存储单元可以被布置在对应的字线和对应的位线的交叉点处。 该设备可以包括位线电压设置电路，用于将要编程的给定存储器单元的位线上的电压设置为可变位线电压或接地电压。 可变位线电压产生电路可以设置在闪存器件中，用于产生可变位线电压。 为了便于设备的编程，可以基于设备的电源电压来设置要编程的给定存储器单元的位线电压，以便基于设定的位线电压维持高于给定阈值电压的电压差 。

公开(公告)号：US20070028155A1

公开(公告)日：2007-02-01

申请号：US11363030

申请日：2006-02-28

申请人： Moo-Sung Kim ,  Seung-Jae Lee

发明人： Moo-Sung Kim ,  Seung-Jae Lee

IPC分类号： H03M13/00

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5622 ,  G11C2216/14

摘要： A flash memory device is disclosed that comprises memory cells, a sense node connected to a selected bit line, a sense circuit configured to selectively provide a first voltage to a common node in accordance with a voltage level of the sense node, a first register connected to the sense node and the common node and configured to store data in accordance with a voltage level of the common node,a second register configured to store data in accordance with the voltage level of the sense node, a switch configured to provide a second voltage to the second register, and a discharge circuit configured to selectively discharge the sense node in accordance with the data stored in the second register.

摘要翻译： 公开了一种闪速存储器件，其包括存储器单元，连接到所选位线的感测节点，感测电路，被配置为根据感测节点的电压电平有选择地向公共节点提供第一电压;第一寄存器连接 到所述感测节点和所述公共节点，并且被配置为根据所述公共节点的电压电平来存储数据;第二寄存器，被配置为根据所述感测节点的电压电平来存储数据;被配置为提供第二电压 以及放电电路，其被配置为根据存储在第二寄存器中的数据选择性地放电感测节点。

公开(公告)号：US07673220B2

公开(公告)日：2010-03-02

申请号：US11363030

申请日：2006-02-28

申请人： Moo-Sung Kim ,  Seung-Jae Lee

发明人： Moo-Sung Kim ,  Seung-Jae Lee

IPC分类号： G11C29/00

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5622 ,  G11C2216/14

摘要： A flash memory device is disclosed that comprises memory cells, a sense node connected to a selected bit line, a sense circuit configured to selectively provide a first voltage to a common node in accordance with a voltage level of the sense node, a first register connected to the sense node and the common node and configured to store data in accordance with a voltage level of the common node, a second register configured to store data in accordance with the voltage level of the sense node, a switch configured to provide a second voltage to the second register, and a discharge circuit configured to selectively discharge the sense node in accordance with the data stored in the second register.

摘要翻译： 公开了一种闪速存储器件，其包括存储器单元，连接到所选位线的感测节点，感测电路，被配置为根据感测节点的电压电平有选择地向公共节点提供第一电压;第一寄存器连接 到所述感测节点和所述公共节点，并且被配置为根据所述公共节点的电压电平来存储数据;第二寄存器，被配置为根据所述感测节点的电压电平来存储数据;被配置为提供第二电压 以及放电电路，其被配置为根据存储在第二寄存器中的数据选择性地放电感测节点。

公开(公告)号：US20050006692A1

公开(公告)日：2005-01-13

申请号：US10840580

申请日：2004-05-07

申请人： Moo-Sung Kim ,  Yeong-Taek Lee ,  Seung-Jae Lee

发明人： Moo-Sung Kim ,  Yeong-Taek Lee ,  Seung-Jae Lee

IPC分类号： G11C16/06 ,  G11C8/00 ,  G11C11/56 ,  G11C16/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  H01L27/115

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  H01L27/115

摘要： A flash memory device may include a memory cell array having a plurality of word lines, bit lines, and memory cells. Each memory cell may be arranged at an intersection of a corresponding word line and a corresponding bit line. The device may include a bit line voltage setting circuit for setting a voltage on a bit line of a given memory cell to be programmed to a variable bit line voltage or to a ground voltage. A variable bit line voltage generating circuit may be provided in the flash memory device for generating the variable bit line voltage. To facilitating programming of the device, a bit line voltage of a given memory cell to be programmed may be set based on a supply voltage of the device, so as to maintain a voltage difference based on the set bit line voltage above a given threshold voltage.

摘要翻译： 闪存器件可以包括具有多个字线，位线和存储器单元的存储单元阵列。 每个存储单元可以被布置在对应的字线和对应的位线的交叉点处。 该设备可以包括位线电压设置电路，用于将要编程的给定存储器单元的位线上的电压设置为可变位线电压或接地电压。 可变位线电压产生电路可以设置在闪存器件中，用于产生可变位线电压。 为了便于设备的编程，可以基于设备的电源电压来设置要编程的给定存储器单元的位线电压，以便基于设定的位线电压维持高于给定阈值电压的电压差 。

公开(公告)号：US08811086B2

公开(公告)日：2014-08-19

申请号：US12458089

申请日：2009-06-30

申请人： Moo-Sung Kim

发明人： Moo-Sung Kim

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12

CPC分类号： G11C16/30 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3427 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/1202

摘要： A flash memory device including a controller to determine higher, M, and lower, N, word-line address bits based on an input word-line address, to determine a selected area of a memory array based on the higher and lower word-line address bits, and an unselected area of the memory array based on the selected area; and a high voltage generator to provide a first pass voltage to a word line of the selected area, and to provide a second pass voltage to a word line of the unselected area. The pass voltages are discriminately applied to the programmed and non-programmed memory cells, enlarging the pass voltage window. The memory array is divided into pluralities of zones to which local voltages are each applied in different levels.

摘要翻译： 一种闪速存储装置，包括：控制器，用于基于输入字线地址确定较高的M，和N个字线地址位，以基于较高和较低字线确定存储器阵列的选定区域 地址位和基于所选区域的存储器阵列的未选择区域; 以及高电压发生器，用于向选定区域的字线提供第一通过电压，并向未选择区域的字线提供第二通过电压。 通过电压被区分地施加到已编程和非编程的存储器单元，扩大通过电压窗口。 存储器阵列被分成多个区域，每个区域各自以不同的级别施加局部电压。

公开(公告)号：US08218365B2

公开(公告)日：2012-07-10

申请号：US12407393

申请日：2009-03-19

申请人： Moo-Sung Kim ,  Young-Ho Lim

发明人： Moo-Sung Kim ,  Young-Ho Lim

IPC分类号： G11C11/40

CPC分类号： G11C16/0483 ,  G11C11/5642 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5634

摘要： Disclosed is a flash memory device having multiple strings, where each string includes first memory cells and second memory cells. One second memory cell of the second memory cells in each string is set to a programmed state, and remaining second memory cells are set to an erased state.

摘要翻译： 公开了一种具有多个串的闪速存储器件，其中每个串包括第一存储器单元和第二存储器单元。 每个串中的第二存储单元的一秒存储单元被设置为编程状态，剩余的第二存储单元被设置为擦除状态。

公开(公告)号：US20110256314A1

公开(公告)日：2011-10-20

申请号：US12904461

申请日：2010-10-14

申请人： Sergei Vladimirovich Ivanov ,  Xinjian Lei ,  Hansong Cheng ,  Daniel P. Spence ,  Moo-Sung Kim

发明人： Sergei Vladimirovich Ivanov ,  Xinjian Lei ,  Hansong Cheng ,  Daniel P. Spence ,  Moo-Sung Kim

IPC分类号： C23C16/18

CPC分类号： C23C16/45553 ,  C07F7/003 ,  C23C16/405

摘要： A method for forming metal-containing films by atomic layer deposition using precursors of the formula: M(OR1)(OR2)(R3C(O)C(R4)C(O)XR5y)2 wherein M is Group 4 metals; wherein R1 and R2 can be same or different selected from the group consisting of a linear or branched C1-10 alkyl and a C6-12 aryl; R3 can be selected from the group consisting of linear or branched C1-10 alkyls, preferably C1-3 alkyls and a C6-12 aryl; R4 is selected from the group consisting of hydrogen, C1-10 alkyls, and a C6-12 aryl, preferably hydrogen; R5 is selected from the group consisting of C1-10 linear or branched alkyls, and a C6-12 aryl, preferably a methyl or ethyl group; X═O or N wherein when X═O, y=1 and R1, 2 and 5 are the same, when X═N, y=2 and each R5 can be the same or different.

摘要翻译： 使用下式的M（OR1）（OR2）（R3C（O）C（R4）C（O）XR5y）2的前体通过原子层沉积形成含金属膜的方法，其中M是第4族金属; 其中R1和R2可以相同或不同，选自直链或支链C 1-10烷基和C 6-12芳基; R 3可以选自直链或支链C 1-10烷基，优选C 1-3烷基和C 6-12芳基; R 4选自氢，C 1-10烷基和C 6-12芳基，优选氢; R5选自C1-10直链或支链烷基，和C6-12芳基，优选甲基或乙基; X = O或N，其中当X = O，y = 1且R 1，2和5相同时，当X = N，y = 2，并且每个R 5可以相同或不同时。

公开(公告)号：US08027208B2

公开(公告)日：2011-09-27

申请号：US12457487

申请日：2009-06-12

申请人： Moo-Sung Kim

发明人： Moo-Sung Kim

IPC分类号： G11C7/00

CPC分类号： G11C16/10 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3427 ,  G11C29/02 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028 ,  G11C2029/1202

摘要： The flash memory device includes a memory cell array having a plurality of memory cells, a high voltage generator configured to generate a plurality of pass voltages, with a first pass voltage of the plurality of pass voltages supplied to the memory cell array during a programming operation; and a main controller including a voltage controller configured to shift the first pass voltage at a plurality of time intervals during the programming operation.

摘要翻译： 闪速存储器件包括具有多个存储单元的存储单元阵列，被配置为产生多个通过电压的高电压发生器，其中在编程操作期间提供给存储单元阵列的多个通过电压的第一通过电压 ; 以及主控制器，其包括电压控制器，其被配置为在编程操作期间以多个时间间隔移位第一通过电压。

公开(公告)号：US07804712B2

公开(公告)日：2010-09-28

申请号：US12216593

申请日：2008-07-08

申请人： Moo-Sung Kim ,  Young-Ho Lim

发明人： Moo-Sung Kim ,  Young-Ho Lim

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/10 ,  G11C16/3427

摘要： A method of programming a flash memory includes programming memory cells connected to a selected word line by applying a first voltage to the selected word line and a second voltage to non-selected word lines, the second voltage being lower than the first voltage, lowering the first voltage of the selected word line to a third voltage after programming the memory cells connected to the selected word line, the third voltage being lower than the first voltage, and recovering a fourth voltage of the selected word line and the non-selected word lines, the fourth voltage being lower than the second and third voltages.

摘要翻译： 一种对闪存进行编程的方法包括通过向所选择的字线施加第一电压并将第二电压施加到未选择的字线来连接到所选字线的编程存储单元，所述第二电压低于所述第一电压， 在对连接到所选字线的存储单元进行编程之后，所选字线的第一电压为第三电压，第三电压低于第一电压，并且恢复所选字线和未选字线的第四电压 ，第四电压低于第二和第三电压。

公开(公告)号：US20100143607A1

公开(公告)日：2010-06-10

申请号：US12629416

申请日：2009-12-02

申请人： Xinjian Lei ,  Daniel P. Spence ,  Moo-Sung Kim ,  Iain Buchanan ,  Laura M. Matz ,  Sergei Vladimirovich Ivanov

发明人： Xinjian Lei ,  Daniel P. Spence ,  Moo-Sung Kim ,  Iain Buchanan ,  Laura M. Matz ,  Sergei Vladimirovich Ivanov

IPC分类号： C23C16/50 ,  C23C16/44 ,  C23C16/22

CPC分类号： C23C16/455 ,  C07F7/003 ,  C23C16/18 ,  C23C16/40

摘要： Described herein are Group 4 metal-containing precursors, compositions comprising Group 4 metal-containing precursors, and deposition processes for fabricating conformal metal containing films on substrates. In one aspect, the Group 4 metal-containing precursors are represented by the following formula I: wherein M comprises a metal chosen from Ti, Zr, and Hf; R and R1 are each independently selected from an alkyl group comprising from 1 to 10 carbon atoms; R2 is an alkyl group comprising from 1 to 10 carbon atoms; R3 is chosen from hydrogen or an alkyl group comprising from 1 to 3 carbon atoms; R4 is an alkyl group comprising from 1 to 6 carbon atoms and wherein R2 and R4 are different alkyl groups. Also described herein are methods for making Group 4 metal-containing precursors and methods for depositing films using the Group 4 metal-containing precursors.

摘要翻译： 本文描述的是含有第4族金属的前体，包含第4族金属的前体的组合物，以及用于在基材上制造含适形金属的膜的沉积工艺。 一方面，含4族金属的前体由下式I表示：其中M包括选自Ti，Zr和Hf的金属; R和R 1各自独立地选自包含1至10个碳原子的烷基; R 2是包含1至10个碳原子的烷基; R3选自氢或包含1至3个碳原子的烷基; R4是包含1至6个碳原子的烷基，其中R2和R4是不同的烷基。 本文还描述了制备含有第4族金属的前体的方法以及使用含有第4族金属的前体沉积膜的方法。