- 专利标题: Scan friendly domino exit and domino entry sequential circuits
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申请号: US11201559申请日: 2005-08-11
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公开(公告)号: US20070035331A1公开(公告)日: 2007-02-15
- 发明人: Mondira Pant , Paul Gronowski , Randy Allmon , Manjunath Bhat , David Lin
- 申请人: Mondira Pant , Paul Gronowski , Randy Allmon , Manjunath Bhat , David Lin
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 主分类号: H03K19/096
- IPC分类号: H03K19/096
摘要:
A circuit for converting received domino logic signals to a static output signal includes a pair of logic gates having inputs and outputs that are cross-coupled and responsive to a domino logic input signal and a clock signal to latch the input signal during an evaluation phase defined by the clock signal. A static output is based on the latched value. One of the logic gates is tri-stateable to establish a value at the static output during a scan mode. A circuit for converting received static logic signals into domino logic signals includes a latch responsive to a clock signal to latch the value of a data signal at a predefined clock transition. A conversion circuit produces a domino logic output signal in response to the clock signal and the latched value of the data signal. A latch component is tri-stateable to establish a value at the output.
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